sys/external/isc/atheros_hal/dist/ar5416/ar5416_interrupts.c

   1 /*
   2  * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
   3  * Copyright (c) 2002-2008 Atheros Communications, Inc.
   4  *
   5  * Permission to use, copy, modify, and/or distribute this software for any
   6  * purpose with or without fee is hereby granted, provided that the above
   7  * copyright notice and this permission notice appear in all copies.
   8  *
   9  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  10  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  11  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  12  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  13  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  14  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  15  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  16  *
  17  * $Id: ar5416_interrupts.c,v 1.1.1.1 2008/12/11 04:46:48 alc Exp $
  18  */
  19 #include "opt_ah.h"
  20
  21 #include "ah.h"
  22 #include "ah_internal.h"
  23
  24 #include "ar5416/ar5416.h"
  25 #include "ar5416/ar5416reg.h"
  26
  27 /*
  28  * Checks to see if an interrupt is pending on our NIC
  29  *
  30  * Returns: TRUE    if an interrupt is pending
  31  *          FALSE   if not
  32  */
  33 HAL_BOOL
  34 ar5416IsInterruptPending(struct ath_hal *ah)
  35 {
  36         uint32_t isr;
  37         /*
  38          * Some platforms trigger our ISR before applying power to
  39          * the card, so make sure the INTPEND is really 1, not 0xffffffff.
  40          */
  41         isr = OS_REG_READ(ah, AR_INTR_ASYNC_CAUSE);
  42         if (isr != AR_INTR_SPURIOUS && (isr & AR_INTR_MAC_IRQ) != 0)
  43                 return AH_TRUE;
  44
  45         isr = OS_REG_READ(ah, AR_INTR_SYNC_CAUSE);
  46         if (isr != AR_INTR_SPURIOUS && (isr & AR_INTR_SYNC_DEFAULT))
  47                 return AH_TRUE;
  48
  49         return AH_FALSE;
  50 }
  51
  52 /*
  53  * Reads the Interrupt Status Register value from the NIC, thus deasserting
  54  * the interrupt line, and returns both the masked and unmasked mapped ISR
  55  * values.  The value returned is mapped to abstract the hw-specific bit
  56  * locations in the Interrupt Status Register.
  57  *
  58  * Returns: A hardware-abstracted bitmap of all non-masked-out
  59  *          interrupts pending, as well as an unmasked value
  60  */
  61 HAL_BOOL
  62 ar5416GetPendingInterrupts(struct ath_hal *ah, HAL_INT *masked)
  63 {
  64         uint32_t isr, isr0, isr1, sync_cause;
  65
  66         /*
  67          * Verify there's a mac interrupt and the RTC is on.
  68          */
  69         if ((OS_REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) &&
  70             (OS_REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M) == AR_RTC_STATUS_ON)
  71                 isr = OS_REG_READ(ah, AR_ISR);
  72         else
  73                 isr = 0;
  74         sync_cause = OS_REG_READ(ah, AR_INTR_SYNC_CAUSE);
  75         sync_cause &= AR_INTR_SYNC_DEFAULT;
  76         if (isr == 0 && sync_cause == 0) {
  77                 *masked = 0;
  78                 return AH_FALSE;
  79         }
  80
  81         if (isr != 0) {
  82                 struct ath_hal_5212 *ahp = AH5212(ah);
  83                 uint32_t mask2;
  84
  85                 mask2 = 0;
  86                 if (isr & AR_ISR_BCNMISC) {
  87                         uint32_t isr2 = OS_REG_READ(ah, AR_ISR_S2);
  88                         if (isr2 & AR_ISR_S2_TIM)
  89                                 mask2 |= HAL_INT_TIM;
  90                         if (isr2 & AR_ISR_S2_DTIM)
  91                                 mask2 |= HAL_INT_DTIM;
  92                         if (isr2 & AR_ISR_S2_DTIMSYNC)
  93                                 mask2 |= HAL_INT_DTIMSYNC;
  94                         if (isr2 & (AR_ISR_S2_CABEND ))
  95                                 mask2 |= HAL_INT_CABEND;
  96                         if (isr2 & AR_ISR_S2_GTT)
  97                                 mask2 |= HAL_INT_GTT;
  98                         if (isr2 & AR_ISR_S2_CST)
  99                                 mask2 |= HAL_INT_CST;
 100                         if (isr2 & AR_ISR_S2_TSFOOR)
 101                                 mask2 |= HAL_INT_TSFOOR;
 102                 }
 103
 104                 isr = OS_REG_READ(ah, AR_ISR_RAC);
 105                 if (isr == 0xffffffff) {
 106                         *masked = 0;
 107                         return AH_FALSE;;
 108                 }
 109
 110                 *masked = isr & HAL_INT_COMMON;
 111                 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
 112                         *masked |= HAL_INT_RX;
 113                 if (isr & (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR | AR_ISR_TXEOL)) {
 114                         *masked |= HAL_INT_TX;
 115                         isr0 = OS_REG_READ(ah, AR_ISR_S0_S);
 116                         ahp->ah_intrTxqs |= MS(isr0, AR_ISR_S0_QCU_TXOK);
 117                         ahp->ah_intrTxqs |= MS(isr0, AR_ISR_S0_QCU_TXDESC);
 118                         isr1 = OS_REG_READ(ah, AR_ISR_S1_S);
 119                         ahp->ah_intrTxqs |= MS(isr1, AR_ISR_S1_QCU_TXERR);
 120                         ahp->ah_intrTxqs |= MS(isr1, AR_ISR_S1_QCU_TXEOL);
 121                 }
 122
 123                 /* Interrupt Mitigation on AR5416 */
 124 #ifdef AR5416_INT_MITIGATION
 125                 if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
 126                         *masked |= HAL_INT_RX;
 127                 if (isr & (AR_ISR_TXMINTR | AR_ISR_TXINTM))
 128                         *masked |= HAL_INT_TX;
 129 #endif
 130                 *masked |= mask2;
 131         }
 132         if (sync_cause != 0) {
 133                 if (sync_cause & (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR)) {
 134                         *masked |= HAL_INT_FATAL;
 135                 }
 136                 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
 137                         HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RADM CPL timeout\n",
 138                             __func__);
 139                         OS_REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
 140                         OS_REG_WRITE(ah, AR_RC, 0);
 141                         *masked |= HAL_INT_FATAL;
 142                 }
 143                 /*
 144                  * On fatal errors collect ISR state for debugging.
 145                  */
 146                 if (*masked & HAL_INT_FATAL) {
 147                         AH_PRIVATE(ah)->ah_fatalState[0] = isr;
 148                         AH_PRIVATE(ah)->ah_fatalState[1] = sync_cause;
 149                         HALDEBUG(ah, HAL_DEBUG_ANY,
 150                             "%s: fatal error, ISR_RAC 0x%x SYNC_CAUSE 0x%x\n",
 151                             __func__, isr, sync_cause);
 152                 }
 153
 154                 OS_REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
 155                 /* NB: flush write */
 156                 (void) OS_REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
 157         }
 158         return AH_TRUE;
 159 }
 160
 161 /*
 162  * Atomically enables NIC interrupts.  Interrupts are passed in
 163  * via the enumerated bitmask in ints.
 164  */
 165 HAL_INT
 166 ar5416SetInterrupts(struct ath_hal *ah, HAL_INT ints)
 167 {
 168         struct ath_hal_5212 *ahp = AH5212(ah);
 169         uint32_t omask = ahp->ah_maskReg;
 170         uint32_t mask,mask2;
 171
 172         HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: 0x%x => 0x%x\n",
 173             __func__, omask, ints);
 174
 175         if (omask & HAL_INT_GLOBAL) {
 176                 HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: disable IER\n", __func__);
 177                 OS_REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
 178                 (void) OS_REG_READ(ah, AR_IER);
 179
 180                 OS_REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
 181                 (void) OS_REG_READ(ah, AR_INTR_ASYNC_ENABLE);
 182
 183                 OS_REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
 184                 (void) OS_REG_READ(ah, AR_INTR_SYNC_ENABLE);
 185         }
 186
 187         mask = ints & HAL_INT_COMMON;
 188         mask2 = 0;
 189
 190         if (ints & HAL_INT_TX) {
 191                 if (ahp->ah_txOkInterruptMask)
 192                         mask |= AR_IMR_TXOK;
 193                 if (ahp->ah_txErrInterruptMask)
 194                         mask |= AR_IMR_TXERR;
 195                 if (ahp->ah_txDescInterruptMask)
 196                         mask |= AR_IMR_TXDESC;
 197                 if (ahp->ah_txEolInterruptMask)
 198                         mask |= AR_IMR_TXEOL;
 199         }
 200         if (ints & HAL_INT_RX)
 201                 mask |= AR_IMR_RXOK | AR_IMR_RXERR | AR_IMR_RXDESC;
 202 #ifdef AR5416_INT_MITIGATION
 203         /*
 204          * Overwrite default mask if Interrupt mitigation
 205          * is specified for AR5416
 206          */
 207         mask = ints & HAL_INT_COMMON;
 208         if (ints & HAL_INT_TX)
 209                 mask |= AR_IMR_TXMINTR | AR_IMR_TXINTM;
 210         if (ints & HAL_INT_RX)
 211                 mask |= AR_IMR_RXERR | AR_IMR_RXMINTR | AR_IMR_RXINTM;
 212 #endif
 213         if (ints & (HAL_INT_BMISC)) {
 214                 mask |= AR_IMR_BCNMISC;
 215                 if (ints & HAL_INT_TIM)
 216                         mask2 |= AR_IMR_S2_TIM;
 217                 if (ints & HAL_INT_DTIM)
 218                         mask2 |= AR_IMR_S2_DTIM;
 219                 if (ints & HAL_INT_DTIMSYNC)
 220                         mask2 |= AR_IMR_S2_DTIMSYNC;
 221                 if (ints & HAL_INT_CABEND)
 222                         mask2 |= (AR_IMR_S2_CABEND );
 223                 if (ints & HAL_INT_GTT)
 224                         mask2 |= AR_IMR_S2_GTT;
 225                 if (ints & HAL_INT_CST)
 226                         mask2 |= AR_IMR_S2_CST;
 227                 if (ints & HAL_INT_TSFOOR)
 228                         mask2 |= AR_IMR_S2_TSFOOR;
 229         }
 230
 231         /* Write the new IMR and store off our SW copy. */
 232         HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: new IMR 0x%x\n", __func__, mask);
 233         OS_REG_WRITE(ah, AR_IMR, mask);
 234         mask = OS_REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM |
 235                                         AR_IMR_S2_DTIM |
 236                                         AR_IMR_S2_DTIMSYNC |
 237                                         AR_IMR_S2_CABEND |
 238                                         AR_IMR_S2_CABTO  |
 239                                         AR_IMR_S2_TSFOOR |
 240                                         AR_IMR_S2_GTT |
 241                                         AR_IMR_S2_CST);
 242         OS_REG_WRITE(ah, AR_IMR_S2, mask | mask2);
 243
 244         ahp->ah_maskReg = ints;
 245
 246         /* Re-enable interrupts if they were enabled before. */
 247         if (ints & HAL_INT_GLOBAL) {
 248                 HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: enable IER\n", __func__);
 249                 OS_REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
 250
 251                 OS_REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, AR_INTR_MAC_IRQ);
 252                 OS_REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
 253
 254                 OS_REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
 255                 OS_REG_WRITE(ah, AR_INTR_SYNC_MASK, AR_INTR_SYNC_DEFAULT);
 256         }
 257
 258         return omask;
 259 }