sys/arch/acorn32/podulebus/escreg.h

   1 /* $NetBSD: escreg.h,v 1.1 1996/10/15 00:05:06 mark Exp $ */
   2
   3 /*
   4  * Copyright (c) 1995 Daniel Widenfalk
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  * 3. All advertising materials mentioning features or use of this software
  15  *    must display the following acknowledgement:
  16  *      This product includes software developed by Daniel Widenfalk
  17  *      for the NetBSD Project.
  18  * 4. The name of the author may not be used to endorse or promote products
  19  *    derived from this software without specific prior written permission
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  22  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  23  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  24  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  25  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  26  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  27  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  28  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  29  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  30  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31  */
  32
  33 #ifndef _ESCREG_H_
  34 #define _ESCREG_H_
  35
  36 /*
  37  * AMD AM53CF94 SCSI interface hardware description.
  38  */
  39
  40 typedef volatile unsigned char vu_char;
  41
  42 typedef struct {
  43         vu_char         *esc_tc_low;    /* rw: Transfer count low */
  44         vu_char         *esc_tc_mid;    /* rw: Transfer count mid */
  45         vu_char         *esc_fifo;      /* rw: Data FIFO */
  46         vu_char         *esc_command;   /* rw: Chip command reg */
  47         vu_char         *esc_dest_id;   /* w: (Re)select bus ID */
  48 #define esc_status esc_dest_id  /* r: Status */
  49         vu_char         *esc_timeout;   /* w: (Re)select timeout */
  50 #define esc_interrupt esc_timeout       /* r: Interrupt */
  51         vu_char         *esc_syncper;   /* w: Synch. transfer period */
  52 #define esc_seqstep esc_syncper /* r: Sequence step */
  53         vu_char         *esc_syncoff;   /* w: Synch. transfer offset */
  54 #define esc_fifo_flags esc_syncoff      /* r: FIFO flags */
  55         vu_char         *esc_config1;   /* rw: Config register #1 */
  56         vu_char         *esc_clkconv;   /* w: Clock conv. factor */
  57         vu_char         *esc_test;      /* w: Test register */
  58         vu_char         *esc_config2;   /* rw: Config register #2 */
  59         vu_char         *esc_config3;   /* rw: Config register #3 */
  60         vu_char         *esc_config4;   /* rw: Config register #4 */
  61         vu_char         *esc_tc_high;   /* rw: Transfer count high */
  62         vu_char         *esc_fifo_bot;  /* w: FIFO bottom register */
  63 } esc_regmap_t;
  64 typedef esc_regmap_t *esc_regmap_p;
  65
  66 /* Commands for the FAS216 */
  67 #define ESC_CMD_DMA                     0x80
  68
  69 #define ESC_CMD_SEL_NO_ATN              0x41
  70 #define ESC_CMD_SEL_ATN         0x42
  71 #define ESC_CMD_SEL_ATN3                0x46
  72 #define ESC_CMD_SEL_ATN_STOP            0x43
  73
  74 #define ESC_CMD_ENABLE_RESEL            0x44
  75 #define ESC_CMD_DISABLE_RESEL           0x45
  76
  77 #define ESC_CMD_TRANSFER_INFO           0x10
  78 #define ESC_CMD_TRANSFER_PAD            0x98
  79
  80 #define ESC_CMD_COMMAND_COMPLETE        0x11
  81 #define ESC_CMD_MESSAGE_ACCEPTED        0x12
  82
  83 #define ESC_CMD_SET_ATN         0x1A
  84 #define ESC_CMD_RESET_ATN               0x1B
  85
  86 #define ESC_CMD_NOP                     0x00
  87 #define ESC_CMD_FLUSH_FIFO              0x01
  88 #define ESC_CMD_RESET_CHIP              0x02
  89 #define ESC_CMD_RESET_SCSI_BUS          0x03
  90
  91 #define ESC_STAT_PHASE_MASK             0x07
  92 #define ESC_STAT_PHASE_TRANS_CPLT       0x08
  93 #define ESC_STAT_TRANSFER_COUNT_ZERO    0x10
  94 #define ESC_STAT_PARITY_ERROR           0x20
  95 #define ESC_STAT_GROSS_ERROR            0x40
  96 #define ESC_STAT_INTERRUPT_PENDING      0x80
  97
  98 #define ESC_PHASE_DATA_OUT              0
  99 #define ESC_PHASE_DATA_IN               1
 100 #define ESC_PHASE_COMMAND               2
 101 #define ESC_PHASE_STATUS                3
 102 #define ESC_PHASE_MESSAGE_OUT           6
 103 #define ESC_PHASE_MESSAGE_IN            7
 104
 105 #define ESC_DEST_ID_MASK                0x07
 106
 107 #define ESC_INT_SELECTED                0x01
 108 #define ESC_INT_SELECTED_WITH_ATN       0x02
 109 #define ESC_INT_RESELECTED              0x04
 110 #define ESC_INT_FUNCTION_COMPLETE       0x08
 111 #define ESC_INT_BUS_SERVICE             0x10
 112 #define ESC_INT_DISCONNECT              0x20
 113 #define ESC_INT_ILLEGAL_COMMAND 0x40
 114 #define ESC_INT_SCSI_RESET_DETECTED     0x80
 115
 116 #define ESC_SYNCHRON_PERIOD_MASK        0x1F
 117
 118 #define ESC_FIFO_COUNT_MASK             0x1F
 119 #define ESC_FIFO_SEQUENCE_STEP_MASK     0xE0
 120 #define ESC_FIFO_SEQUENCE_SHIFT 5
 121
 122 #define ESC_SYNCHRON_OFFSET_MASK        0x0F
 123 #define ESC_SYNC_ASSERT_MASK            0x30
 124 #define ESC_SYNC_ASSERT_SHIFT           4
 125 #define ESC_SYNC_DEASSERT_MASK          0x30
 126 #define ESC_SYNC_DEASSERT_SHIFT 6
 127
 128 #define ESC_CFG1_BUS_ID_MASK            0x07
 129 #define ESC_CFG1_CHIP_TEST_MODE 0x08
 130 #define ESC_CFG1_SCSI_PARITY_ENABLE     0x10
 131 #define ESC_CFG1_PARITY_TEST_MODE       0x20
 132 #define ESC_CFG1_SCSI_RES_INT_DIS       0x40
 133 #define ESC_CFG1_SLOW_CABLE_MODE        0x80
 134
 135 #define ESC_CLOCK_CONVERSION_MASK       0x07
 136
 137 #define ESC_TEST_TARGET_TEST_MODE       0x01
 138 #define ESC_TEST_INITIATOR_TEST_MODE    0x02
 139 #define ESC_TEST_TRISTATE_TEST_MODE     0x04
 140
 141 #define ESC_CFG2_DMA_PARITY_ENABLE      0x01
 142 #define ESC_CFG2_REG_PARITY_ENABLE      0x02
 143 #define ESC_CFG2_TARG_BAD_PARITY_ABORT  0x04
 144 #define ESC_CFG2_SCSI_2_MODE            0x08
 145 #define ESC_CFG2_TRISTATE_DMA_REQ       0x10
 146 #define ESC_CFG2_BYTE_CONTROL_MODE      0x20
 147 #define ESC_CFG2_FEATURES_ENABLE        0x40
 148 #define ESC_CFG2_RESERVE_FIFO_BYTE      0x80
 149
 150 #define ESC_CFG3_THRESHOLD_8_MODE       0x01
 151 #define ESC_CFG3_ALTERNATE_DMA_MODE     0x02
 152 #define ESC_CFG3_SAVE_RESIDUAL_BYTE     0x04
 153 #define ESC_CFG3_FASTCLK                0x08
 154 #define ESC_CFG3_FASTSCSI               0x10
 155 #define ESC_CFG3_CDB10                  0x20
 156 #define ESC_CFG3_QENB                   0x40
 157 #define ESC_CFG3_IDRESCHK               0x80
 158
 159 #define ESC_CFG4_RADE                   0x04
 160 #define ESC_CFG4_RAE                    0x08
 161 #define ESC_CFG4_POWERDOWN              0x20
 162 #define ESC_CFG4_GLITCH_EATER_0         0x40
 163 #define ESC_CFG4_GLITCH_EATER_1         0x80
 164
 165 #endif