sys/arch/acorn32/podulebus/sfasreg.h

   1 /* $NetBSD: sfasreg.h,v 1.1 1996/01/31 23:26:45 mark Exp $ */
   2
   3 /*
   4  * Copyright (c) 1995 Daniel Widenfalk
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  * 3. All advertising materials mentioning features or use of this software
  15  *    must display the following acknowledgement:
  16  *      This product includes software developed by Daniel Widenfalk
  17  *      for the NetBSD Project.
  18  * 4. The name of the author may not be used to endorse or promote products
  19  *    derived from this software without specific prior written permission
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  22  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  23  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  24  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  25  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  26  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  27  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  28  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  29  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  30  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31  */
  32
  33 #ifndef _SFASREG_H_
  34 #define _SFASREG_H_
  35
  36 /*
  37  * Emulex FAS216 SCSI interface hardware description.
  38  */
  39
  40 typedef volatile unsigned char vu_char;
  41
  42 typedef struct {
  43         vu_char         *sfas_tc_low;   /* rw: Transfer count low */
  44         vu_char         *sfas_tc_mid;   /* rw: Transfer count mid */
  45         vu_char         *sfas_fifo;     /* rw: Data FIFO */
  46         vu_char         *sfas_command;  /* rw: Chip command reg */
  47         vu_char         *sfas_dest_id;  /* w: (Re)select bus ID */
  48 #define sfas_status sfas_dest_id        /* r: Status */
  49         vu_char         *sfas_timeout;  /* w: (Re)select timeout */
  50 #define sfas_interrupt sfas_timeout     /* r: Interrupt */
  51         vu_char         *sfas_syncper;  /* w: Synch. transfer period */
  52 #define sfas_seqstep sfas_syncper       /* r: Sequence step */
  53         vu_char         *sfas_syncoff;  /* w: Synch. transfer offset */
  54 #define sfas_fifo_flags sfas_syncoff    /* r: FIFO flags */
  55         vu_char         *sfas_config1;  /* rw: Config register #1 */
  56         vu_char         *sfas_clkconv;  /* w: Clock conv. factor */
  57         vu_char         *sfas_test;     /* w: Test register */
  58         vu_char         *sfas_config2;  /* rw: Config register #2 */
  59         vu_char         *sfas_config3;  /* rw: Config register #3 */
  60         vu_char         *sfas_tc_high;  /* rw: Transfer count high */
  61         vu_char         *sfas_fifo_bot; /* w: FIFO bottom register */
  62 } sfas_regmap_t;
  63 typedef sfas_regmap_t *sfas_regmap_p;
  64
  65 /* Commands for the FAS216 */
  66 #define SFAS_CMD_DMA                    0x80
  67
  68 #define SFAS_CMD_SEL_NO_ATN             0x41
  69 #define SFAS_CMD_SEL_ATN                0x42
  70 #define SFAS_CMD_SEL_ATN3               0x46
  71 #define SFAS_CMD_SEL_ATN_STOP           0x43
  72
  73 #define SFAS_CMD_ENABLE_RESEL           0x44
  74 #define SFAS_CMD_DISABLE_RESEL          0x45
  75
  76 #define SFAS_CMD_TRANSFER_INFO          0x10
  77 #define SFAS_CMD_TRANSFER_PAD           0x98
  78
  79 #define SFAS_CMD_COMMAND_COMPLETE       0x11
  80 #define SFAS_CMD_MESSAGE_ACCEPTED       0x12
  81
  82 #define SFAS_CMD_SET_ATN                0x1A
  83 #define SFAS_CMD_RESET_ATN              0x1B
  84
  85 #define SFAS_CMD_NOP                    0x00
  86 #define SFAS_CMD_FLUSH_FIFO             0x01
  87 #define SFAS_CMD_RESET_CHIP             0x02
  88 #define SFAS_CMD_RESET_SCSI_BUS         0x03
  89
  90 #define SFAS_STAT_PHASE_MASK            0x07
  91 #define SFAS_STAT_PHASE_TRANS_CPLT      0x08
  92 #define SFAS_STAT_TRANSFER_COUNT_ZERO   0x10
  93 #define SFAS_STAT_PARITY_ERROR          0x20
  94 #define SFAS_STAT_GROSS_ERROR           0x40
  95 #define SFAS_STAT_INTERRUPT_PENDING     0x80
  96
  97 #define SFAS_PHASE_DATA_OUT             0
  98 #define SFAS_PHASE_DATA_IN              1
  99 #define SFAS_PHASE_COMMAND              2
 100 #define SFAS_PHASE_STATUS               3
 101 #define SFAS_PHASE_MESSAGE_OUT          6
 102 #define SFAS_PHASE_MESSAGE_IN           7
 103
 104 #define SFAS_DEST_ID_MASK               0x07
 105
 106 #define SFAS_INT_SELECTED               0x01
 107 #define SFAS_INT_SELECTED_WITH_ATN      0x02
 108 #define SFAS_INT_RESELECTED             0x04
 109 #define SFAS_INT_FUNCTION_COMPLETE      0x08
 110 #define SFAS_INT_BUS_SERVICE            0x10
 111 #define SFAS_INT_DISCONNECT             0x20
 112 #define SFAS_INT_ILLEGAL_COMMAND        0x40
 113 #define SFAS_INT_SCSI_RESET_DETECTED    0x80
 114
 115 #define SFAS_SYNCHRON_PERIOD_MASK       0x1F
 116
 117 #define SFAS_FIFO_COUNT_MASK            0x1F
 118 #define SFAS_FIFO_SEQUENCE_STEP_MASK    0xE0
 119 #define SFAS_FIFO_SEQUENCE_SHIFT        5
 120
 121 #define SFAS_SYNCHRON_OFFSET_MASK       0x0F
 122 #define SFAS_SYNC_ASSERT_MASK           0x30
 123 #define SFAS_SYNC_ASSERT_SHIFT          4
 124 #define SFAS_SYNC_DEASSERT_MASK         0x30
 125 #define SFAS_SYNC_DEASSERT_SHIFT        6
 126
 127 #define SFAS_CFG1_BUS_ID_MASK           0x07
 128 #define SFAS_CFG1_CHIP_TEST_MODE        0x08
 129 #define SFAS_CFG1_SCSI_PARITY_ENABLE    0x10
 130 #define SFAS_CFG1_PARITY_TEST_MODE      0x20
 131 #define SFAS_CFG1_SCSI_RES_INT_DIS      0x40
 132 #define SFAS_CFG1_SLOW_CABLE_MODE       0x80
 133
 134 #define SFAS_CLOCK_CONVERSION_MASK      0x07
 135
 136 #define SFAS_TEST_TARGET_TEST_MODE      0x01
 137 #define SFAS_TEST_INITIATOR_TEST_MODE   0x02
 138 #define SFAS_TEST_TRISTATE_TEST_MODE    0x04
 139
 140 #define SFAS_CFG2_DMA_PARITY_ENABLE     0x01
 141 #define SFAS_CFG2_REG_PARITY_ENABLE     0x02
 142 #define SFAS_CFG2_TARG_BAD_PARITY_ABORT 0x04
 143 #define SFAS_CFG2_SCSI_2_MODE           0x08
 144 #define SFAS_CFG2_TRISTATE_DMA_REQ      0x10
 145 #define SFAS_CFG2_BYTE_CONTROL_MODE     0x20
 146 #define SFAS_CFG2_FEATURES_ENABLE       0x40
 147 #define SFAS_CFG2_RESERVE_FIFO_BYTE     0x80
 148
 149 #define SFAS_CFG3_THRESHOLD_8_MODE      0x01
 150 #define SFAS_CFG3_ALTERNATE_DMA_MODE    0x02
 151 #define SFAS_CFG3_SAVE_RESIDUAL_BYTE    0x04
 152 #define SFAS_CFG3_FASTCLK               0x08
 153 #define SFAS_CFG3_FASTSCSI              0x10
 154 #define SFAS_CFG3_CDB10                 0x20
 155 #define SFAS_CFG3_QENB                  0x40
 156 #define SFAS_CFG3_IDRESCHK              0x80
 157
 158 #endif