sys/arch/alpha/pci/dwlpx_pci.c

   1 /* $NetBSD: dwlpx_pci.c,v 1.14 2009/03/14 15:35:59 dsl Exp $ */
   2
   3 /*
   4  * Copyright (c) 1997 by Matthew Jacob
   5  * NASA AMES Research Center.
   6  * All rights reserved.
   7  *
   8  * Redistribution and use in source and binary forms, with or without
   9  * modification, are permitted provided that the following conditions
  10  * are met:
  11  * 1. Redistributions of source code must retain the above copyright
  12  *    notice immediately at the beginning of the file, without modification,
  13  *    this list of conditions, and the following disclaimer.
  14  * 2. Redistributions in binary form must reproduce the above copyright
  15  *    notice, this list of conditions and the following disclaimer in the
  16  *    documentation and/or other materials provided with the distribution.
  17  * 3. The name of the author may not be used to endorse or promote products
  18  *    derived from this software without specific prior written permission.
  19  *
  20  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  21  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
  24  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  25  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  26  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  27  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  28  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  29  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  30  * SUCH DAMAGE.
  31  */
  32
  33 #include <sys/cdefs.h>                  /* RCS ID & Copyright macro defns */
  34
  35 __KERNEL_RCSID(0, "$NetBSD: dwlpx_pci.c,v 1.14 2009/03/14 15:35:59 dsl Exp $");
  36
  37 #include <sys/param.h>
  38 #include <sys/systm.h>
  39 #include <sys/kernel.h>
  40 #include <sys/device.h>
  41
  42 #include <uvm/uvm_extern.h>
  43
  44 #include <dev/pci/pcireg.h>
  45 #include <dev/pci/pcivar.h>
  46 #include <alpha/tlsb/tlsbreg.h>
  47 #include <alpha/pci/dwlpxreg.h>
  48 #include <alpha/pci/dwlpxvar.h>
  49
  50 #define KV(_addr)       ((void *)ALPHA_PHYS_TO_K0SEG((_addr)))
  51
  52 void            dwlpx_attach_hook(struct device *, struct device *,
  53                     struct pcibus_attach_args *);
  54 int             dwlpx_bus_maxdevs(void *, int);
  55 pcitag_t        dwlpx_make_tag(void *, int, int, int);
  56 void            dwlpx_decompose_tag(void *, pcitag_t, int *, int *,
  57                     int *);
  58 pcireg_t        dwlpx_conf_read(void *, pcitag_t, int);
  59 void            dwlpx_conf_write(void *, pcitag_t, int, pcireg_t);
  60
  61 void
  62 dwlpx_pci_init(pci_chipset_tag_t pc, void *v)
  63 {
  64         pc->pc_conf_v = v;
  65         pc->pc_attach_hook = dwlpx_attach_hook;
  66         pc->pc_bus_maxdevs = dwlpx_bus_maxdevs;
  67         pc->pc_make_tag = dwlpx_make_tag;
  68         pc->pc_decompose_tag = dwlpx_decompose_tag;
  69         pc->pc_conf_read = dwlpx_conf_read;
  70         pc->pc_conf_write = dwlpx_conf_write;
  71 }
  72
  73 void
  74 dwlpx_attach_hook(struct device *parent, struct device *self, struct pcibus_attach_args *pba)
  75 {
  76 #if     0
  77         struct dwlpx_config *ccp = pba->pba_pc->pc_conf_v;
  78         printf("dwlpx_attach_hook for %s\n", ccp->cc_sc->dwlpx_dev.dv_xname);
  79 #endif
  80 }
  81
  82 int
  83 dwlpx_bus_maxdevs(void *cpv, int busno)
  84 {
  85         return DWLPX_MAXDEV;
  86 }
  87
  88 pcitag_t
  89 dwlpx_make_tag(void *cpv, int b, int d, int f)
  90 {
  91         pcitag_t tag;
  92         int hpcdev, pci_idsel;
  93
  94         pci_idsel = (1 << ((d & 0x3) + 2));
  95         hpcdev = d >> 2;
  96         tag = (b << 24) | (hpcdev << 22) | (pci_idsel << 16) | (f << 13);
  97         return (tag);
  98 }
  99
 100 void
 101 dwlpx_decompose_tag(void *cpv, pcitag_t tag, int *bp, int *dp, int *fp)
 102 {
 103
 104         if (bp != NULL)
 105                 *bp = (tag >> 24) & 0xff;
 106         if (dp != NULL) {
 107                 int j, i = (tag >> 18) & 0xf;
 108                 j = -1;
 109                 while (i != 0) {
 110                         j++;
 111                         i >>= 1;
 112                 }
 113                 j += (((tag >> 22) & 3) << 2);
 114                 *dp = j;
 115         }
 116         if (fp != NULL)
 117                 *fp = (tag >> 13) & 0x7;
 118 }
 119
 120 pcireg_t
 121 dwlpx_conf_read(void *cpv, pcitag_t tag, int offset)
 122 {
 123         struct dwlpx_config *ccp = cpv;
 124         struct dwlpx_softc *sc;
 125         pcireg_t *dp, data = (pcireg_t) -1;
 126         unsigned long paddr;
 127         int secondary, i, s = 0;
 128         u_int32_t rvp;
 129
 130         if (ccp == NULL) {
 131                 panic("NULL ccp in dwlpx_conf_read");
 132         }
 133         sc = ccp->cc_sc;
 134         secondary = tag >> 24;
 135         if (secondary) {
 136                 tag &= 0x1fffff;
 137                 tag |= (secondary << 21);
 138
 139 #if     0
 140                 printf("read secondary %d reg %x (tag %x)",
 141                     secondary, offset, tag);
 142 #endif
 143
 144                 alpha_pal_draina();
 145                 s = splhigh();
 146                 /*
 147                  * Set up HPCs for type 1 cycles.
 148                  */
 149                 for (i = 0; i < sc->dwlpx_nhpc; i++) {
 150                         rvp = REGVAL(PCIA_CTL(i) + ccp->cc_sysbase) |
 151                                 PCIA_CTL_T1CYC;
 152                         alpha_mb();
 153                         REGVAL(PCIA_CTL(i) + ccp->cc_sysbase) = rvp;
 154                         alpha_mb();
 155                 }
 156         }
 157         paddr = (unsigned long) tag;
 158         paddr |= DWLPX_PCI_CONF;
 159         paddr |= ((unsigned long) ((offset >> 2) << 7));
 160         paddr |= (((unsigned long) sc->dwlpx_hosenum) << 34);
 161         paddr |= (((u_long) sc->dwlpx_node - 4) << 36);
 162         paddr |= (1LL << 39);
 163         paddr |= (3LL << 3);    /* 32 Bit PCI byte enables */
 164
 165         dp = (pcireg_t *)KV(paddr);
 166         if (badaddr(dp, sizeof (*dp)) == 0) {
 167                 data = *dp;
 168         }
 169         if (secondary) {
 170                 alpha_pal_draina();
 171                 for (i = 0; i < sc->dwlpx_nhpc; i++) {
 172                         rvp = REGVAL(PCIA_CTL(i) + ccp->cc_sysbase) &
 173                                 ~PCIA_CTL_T1CYC;
 174                         alpha_mb();
 175                         REGVAL(PCIA_CTL(i) + ccp->cc_sysbase) = rvp;
 176                         alpha_mb();
 177                 }
 178                 (void) splx(s);
 179 #if     0
 180                 printf("=%x\n", data);
 181 #endif
 182         }
 183         return (data);
 184 }
 185
 186 void
 187 dwlpx_conf_write(void *cpv, pcitag_t tag, int offset, pcireg_t data)
 188 {
 189         struct dwlpx_config *ccp = cpv;
 190         struct dwlpx_softc *sc;
 191         pcireg_t *dp;
 192         unsigned long paddr;
 193         int secondary, i, s = 0;
 194         u_int32_t rvp;
 195
 196         if (ccp == NULL) {
 197                 panic("NULL ccp in dwlpx_conf_write");
 198         }
 199         sc = ccp->cc_sc;
 200         secondary = tag >> 24;
 201         if (secondary) {
 202                 tag &= 0x1fffff;
 203                 tag |= (secondary << 21);
 204 #if     0
 205                 printf("write secondary %d reg %x (tag %x) with %x\n",
 206                     secondary, offset, tag, data);
 207 #endif
 208
 209                 alpha_pal_draina();
 210                 s = splhigh();
 211                 /*
 212                  * Set up HPCs for type 1 cycles.
 213                  */
 214                 for (i = 0; i < sc->dwlpx_nhpc; i++) {
 215                         rvp = REGVAL(PCIA_CTL(i) + ccp->cc_sysbase) |
 216                                 PCIA_CTL_T1CYC;
 217                         alpha_mb();
 218                         REGVAL(PCIA_CTL(i) + ccp->cc_sysbase) = rvp;
 219                         alpha_mb();
 220                 }
 221         }
 222         paddr = (unsigned long) tag;
 223         paddr |= DWLPX_PCI_CONF;
 224         paddr |= ((unsigned long) ((offset >> 2) << 7));
 225         paddr |= (((unsigned long) sc->dwlpx_hosenum) << 34);
 226         paddr |= (((u_long) sc->dwlpx_node - 4) << 36);
 227         paddr |= (1LL << 39);
 228         paddr |= (3LL << 3);    /* 32 bit PCI byte enables */
 229
 230         dp = (pcireg_t *)KV(paddr);
 231         *dp = data;
 232         alpha_mb();
 233         if (secondary) {
 234                 alpha_pal_draina();
 235                 for (i = 0; i < sc->dwlpx_nhpc; i++) {
 236                         rvp = REGVAL(PCIA_CTL(i) + ccp->cc_sysbase) &
 237                                 ~PCIA_CTL_T1CYC;
 238                         alpha_mb();
 239                         REGVAL(PCIA_CTL(i) + ccp->cc_sysbase) = rvp;
 240                         alpha_mb();
 241                 }
 242                 (void) splx(s);
 243         }
 244 }