sys/arch/amiga/dev/cbscvar.h

   1 /*      $NetBSD: cbscvar.h,v 1.3 2008/04/13 04:55:52 tsutsui Exp $      */
   2
   3 /*
   4  * Copyright (c) 1997 Michael L. Hitch.
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  17  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  18  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  19  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  20  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  21  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  22  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  23  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  24  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  25  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26  */
  27
  28 struct cbsc_softc {
  29         struct ncr53c9x_softc   sc_ncr53c9x;    /* glue to MI code */
  30
  31         struct isr      sc_isr;                 /* Interrupt chain struct */
  32
  33         volatile uint8_t *sc_reg;               /* the registers */
  34         volatile uint8_t *sc_dmabase;
  35
  36         int             sc_active;              /* Pseudo-DMA state vars */
  37         int             sc_datain;
  38         int             sc_tc;
  39         size_t          sc_dmasize;
  40         size_t          sc_dmatrans;
  41         uint8_t         **sc_dmaaddr;
  42         size_t          *sc_pdmalen;
  43         paddr_t         sc_pa;
  44
  45         uint8_t         sc_pad1[18];            /* XXX */
  46         uint8_t         sc_alignbuf[256];
  47         uint8_t         sc_pad2[16];
  48         uint8_t         sc_hardbits;
  49         uint8_t         sc_portbits;
  50         uint8_t         sc_xfr_align;
  51 };
  52
  53 #define CBSC_HB_CREQ            0x80
  54
  55 #define CBSC_PB_LONG            0x20
  56 #define CBSC_PB_WRITE           0x40
  57 #define CBSC_PB_LED             0x80