sys/arch/amiga/dev/grf_cvreg.h

   1 /*      $NetBSD: grf_cvreg.h,v 1.12 2007/03/05 19:48:19 he Exp $        */
   2
   3 /*
   4  * Copyright (c) 1995 Michael Teske
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  * 3. All advertising materials mentioning features or use of this software
  16  *    must display the following acknowledgement:
  17  *      This product includes software developed by Ezra Story, by Kari
  18  *      Mettinen and by Bernd Ernesti.
  19  * 4. The name of the author may not be used to endorse or promote products
  20  *    derived from this software without specific prior written permission
  21  *
  22  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  23  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  24  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  25  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  26  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  27  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  31  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #ifndef _GRF_CVREG_H
  35 #define _GRF_CVREG_H
  36
  37 /*
  38  * This is derived from ciruss driver source
  39  */
  40
  41 /* Extension to grfvideo_mode to support text modes.
  42  * This can be passed to both text & gfx functions
  43  * without worry.  If gv.depth == 4, then the extended
  44  * fields for a text mode are present.
  45  */
  46
  47 struct grfcvtext_mode {
  48         struct grfvideo_mode gv;
  49         unsigned short  fx;     /* font x dimension */
  50         unsigned short  fy;     /* font y dimension */
  51         unsigned short  cols;   /* screen dimensions */
  52         unsigned short  rows;
  53         void            *fdata; /* font data */
  54         unsigned short  fdstart;
  55         unsigned short  fdend;
  56 };
  57
  58 /* maximum console size */
  59 #define MAXROWS 200
  60 #define MAXCOLS 200
  61
  62 /* read VGA register */
  63 #define vgar(ba, reg) (*(((volatile char *)ba)+reg))
  64
  65 /* write VGA register */
  66 #define vgaw(ba, reg, val) \
  67         *(((volatile char *)ba)+reg) = ((val) & 0xff)
  68
  69
  70 /* read 32 Bit VGA register */
  71 #define vgar32(ba, reg) \
  72         (  *((volatile unsigned long *) (((volatile char *)ba)+reg)) )
  73
  74 /* write 32 Bit VGA register */
  75 #define vgaw32(ba, reg, val) \
  76         *((unsigned long *)  (((volatile char *)ba)+reg)) = val
  77
  78 /* read 16 Bit VGA register */
  79 #define vgar16(ba, reg) \
  80         (  *((volatile unsigned short *) (((volatile char *)ba)+reg)) )
  81
  82 /* write 16 Bit VGA register */
  83 #define vgaw16(ba, reg, val) \
  84         *((volatile unsigned short *)  (((volatile char *)ba)+reg)) = val
  85
  86 #ifdef _KERNEL
  87 int grfcv_cnprobe(void);
  88 void grfcv_iteinit(struct grf_softc *);
  89 static inline void GfxBusyWait(volatile void *);
  90 static inline void GfxFifoWait(volatile void *);
  91 static inline unsigned char RAttr(volatile void *, short);
  92 static inline unsigned char RSeq(volatile void *, short);
  93 static inline unsigned char RCrt(volatile void *, short);
  94 static inline unsigned char RGfx(volatile void *, short);
  95 #endif
  96
  97
  98 /*
  99  * defines for the used register addresses (mw)
 100  *
 101  * NOTE: there are some registers that have different addresses when
 102  *       in mono or color mode. We only support color mode, and thus
 103  *       some addresses won't work in mono-mode!
 104  *
 105  * General and VGA-registers taken from retina driver. Fixed a few
 106  * bugs in it. (SR and GR read address is Port + 1, NOT Port)
 107  *
 108  */
 109
 110 /* General Registers: */
 111 #define GREG_MISC_OUTPUT_R      0x03CC
 112 #define GREG_MISC_OUTPUT_W      0x03C2
 113 #define GREG_FEATURE_CONTROL_R  0x03CA
 114 #define GREG_FEATURE_CONTROL_W  0x03DA
 115 #define GREG_INPUT_STATUS0_R    0x03C2
 116 #define GREG_INPUT_STATUS1_R    0x03DA
 117
 118 /* Setup Registers: */
 119 #define SREG_OPTION_SELECT      0x0102
 120 #define SREG_VIDEO_SUBS_ENABLE  0x46E8
 121
 122 /* Attribute Controller: */
 123 #define ACT_ADDRESS             0x03C0
 124 #define ACT_ADDRESS_R           0x03C1
 125 #define ACT_ADDRESS_W           0x03C0
 126 #define ACT_ADDRESS_RESET       0x03DA
 127 #define ACT_ID_PALETTE0         0x00
 128 #define ACT_ID_PALETTE1         0x01
 129 #define ACT_ID_PALETTE2         0x02
 130 #define ACT_ID_PALETTE3         0x03
 131 #define ACT_ID_PALETTE4         0x04
 132 #define ACT_ID_PALETTE5         0x05
 133 #define ACT_ID_PALETTE6         0x06
 134 #define ACT_ID_PALETTE7         0x07
 135 #define ACT_ID_PALETTE8         0x08
 136 #define ACT_ID_PALETTE9         0x09
 137 #define ACT_ID_PALETTE10        0x0A
 138 #define ACT_ID_PALETTE11        0x0B
 139 #define ACT_ID_PALETTE12        0x0C
 140 #define ACT_ID_PALETTE13        0x0D
 141 #define ACT_ID_PALETTE14        0x0E
 142 #define ACT_ID_PALETTE15        0x0F
 143 #define ACT_ID_ATTR_MODE_CNTL   0x10
 144 #define ACT_ID_OVERSCAN_COLOR   0x11
 145 #define ACT_ID_COLOR_PLANE_ENA  0x12
 146 #define ACT_ID_HOR_PEL_PANNING  0x13
 147 #define ACT_ID_COLOR_SELECT     0x14
 148
 149 /* Graphics Controller: */
 150 #define GCT_ADDRESS             0x03CE
 151 #define GCT_ADDRESS_R           0x03CF
 152 #define GCT_ADDRESS_W           0x03CF
 153 #define GCT_ID_SET_RESET        0x00
 154 #define GCT_ID_ENABLE_SET_RESET 0x01
 155 #define GCT_ID_COLOR_COMPARE    0x02
 156 #define GCT_ID_DATA_ROTATE      0x03
 157 #define GCT_ID_READ_MAP_SELECT  0x04
 158 #define GCT_ID_GRAPHICS_MODE    0x05
 159 #define GCT_ID_MISC             0x06
 160 #define GCT_ID_COLOR_XCARE      0x07
 161 #define GCT_ID_BITMASK          0x08
 162
 163 /* Sequencer: */
 164 #define SEQ_ADDRESS             0x03C4
 165 #define SEQ_ADDRESS_R           0x03C5
 166 #define SEQ_ADDRESS_W           0x03C5
 167 #define SEQ_ID_RESET            0x00
 168 #define SEQ_ID_CLOCKING_MODE    0x01
 169 #define SEQ_ID_MAP_MASK         0x02
 170 #define SEQ_ID_CHAR_MAP_SELECT  0x03
 171 #define SEQ_ID_MEMORY_MODE      0x04
 172 #define SEQ_ID_UNKNOWN1         0x05
 173 #define SEQ_ID_UNKNOWN2         0x06
 174 #define SEQ_ID_UNKNOWN3         0x07
 175 /* S3 extensions */
 176 #define SEQ_ID_UNLOCK_EXT       0x08
 177 #define SEQ_ID_EXT_SEQ_REG9     0x09
 178 #define SEQ_ID_BUS_REQ_CNTL     0x0A
 179 #define SEQ_ID_EXT_MISC_SEQ     0x0B
 180 #define SEQ_ID_UNKNOWN4         0x0C
 181 #define SEQ_ID_EXT_SEQ          0x0D
 182 #define SEQ_ID_UNKNOWN5         0x0E
 183 #define SEQ_ID_UNKNOWN6         0x0F
 184 #define SEQ_ID_MCLK_LO          0x10
 185 #define SEQ_ID_MCLK_HI          0x11
 186 #define SEQ_ID_DCLK_LO          0x12
 187 #define SEQ_ID_DCLK_HI          0x13
 188 #define SEQ_ID_CLKSYN_CNTL_1    0x14
 189 #define SEQ_ID_CLKSYN_CNTL_2    0x15
 190 #define SEQ_ID_CLKSYN_TEST_HI   0x16    /* reserved for S3 testing of the */
 191 #define SEQ_ID_CLKSYN_TEST_LO   0x17    /*   internal clock synthesizer   */
 192 #define SEQ_ID_RAMDAC_CNTL      0x18
 193 #define SEQ_ID_MORE_MAGIC       0x1A
 194
 195 /* CRT Controller: */
 196 #define CRT_ADDRESS             0x03D4
 197 #define CRT_ADDRESS_R           0x03D5
 198 #define CRT_ADDRESS_W           0x03D5
 199 #define CRT_ID_HOR_TOTAL        0x00
 200 #define CRT_ID_HOR_DISP_ENA_END 0x01
 201 #define CRT_ID_START_HOR_BLANK  0x02
 202 #define CRT_ID_END_HOR_BLANK    0x03
 203 #define CRT_ID_START_HOR_RETR   0x04
 204 #define CRT_ID_END_HOR_RETR     0x05
 205 #define CRT_ID_VER_TOTAL        0x06
 206 #define CRT_ID_OVERFLOW         0x07
 207 #define CRT_ID_PRESET_ROW_SCAN  0x08
 208 #define CRT_ID_MAX_SCAN_LINE    0x09
 209 #define CRT_ID_CURSOR_START     0x0A
 210 #define CRT_ID_CURSOR_END       0x0B
 211 #define CRT_ID_START_ADDR_HIGH  0x0C
 212 #define CRT_ID_START_ADDR_LOW   0x0D
 213 #define CRT_ID_CURSOR_LOC_HIGH  0x0E
 214 #define CRT_ID_CURSOR_LOC_LOW   0x0F
 215 #define CRT_ID_START_VER_RETR   0x10
 216 #define CRT_ID_END_VER_RETR     0x11
 217 #define CRT_ID_VER_DISP_ENA_END 0x12
 218 #define CRT_ID_SCREEN_OFFSET    0x13
 219 #define CRT_ID_UNDERLINE_LOC    0x14
 220 #define CRT_ID_START_VER_BLANK  0x15
 221 #define CRT_ID_END_VER_BLANK    0x16
 222 #define CRT_ID_MODE_CONTROL     0x17
 223 #define CRT_ID_LINE_COMPARE     0x18
 224 #define CRT_ID_GD_LATCH_RBACK   0x22
 225 #define CRT_ID_ACT_TOGGLE_RBACK 0x24
 226 #define CRT_ID_ACT_INDEX_RBACK  0x26
 227 /* S3 extensions: S3 VGA Registers */
 228 #define CRT_ID_DEVICE_HIGH      0x2D
 229 #define CRT_ID_DEVICE_LOW       0x2E
 230 #define CRT_ID_REVISION         0x2F
 231 #define CRT_ID_CHIP_ID_REV      0x30
 232 #define CRT_ID_MEMORY_CONF      0x31
 233 #define CRT_ID_BACKWAD_COMP_1   0x32
 234 #define CRT_ID_BACKWAD_COMP_2   0x33
 235 #define CRT_ID_BACKWAD_COMP_3   0x34
 236 #define CRT_ID_REGISTER_LOCK    0x35
 237 #define CRT_ID_CONFIG_1         0x36
 238 #define CRT_ID_CONFIG_2         0x37
 239 #define CRT_ID_REGISTER_LOCK_1  0x38
 240 #define CRT_ID_REGISTER_LOCK_2  0x39
 241 #define CRT_ID_MISC_1           0x3A
 242 #define CRT_ID_DISPLAY_FIFO     0x3B
 243 #define CRT_ID_LACE_RETR_START  0x3C
 244 /* S3 extensions: System Control Registers  */
 245 #define CRT_ID_SYSTEM_CONFIG    0x40
 246 #define CRT_ID_BIOS_FLAG        0x41
 247 #define CRT_ID_LACE_CONTROL     0x42
 248 #define CRT_ID_EXT_MODE         0x43
 249 #define CRT_ID_HWGC_MODE        0x45    /* HWGC = Hardware Graphics Cursor */
 250 #define CRT_ID_HWGC_ORIGIN_X_HI 0x46
 251 #define CRT_ID_HWGC_ORIGIN_X_LO 0x47
 252 #define CRT_ID_HWGC_ORIGIN_Y_HI 0x48
 253 #define CRT_ID_HWGC_ORIGIN_Y_LO 0x49
 254 #define CRT_ID_HWGC_FG_STACK    0x4A
 255 #define CRT_ID_HWGC_BG_STACK    0x4B
 256 #define CRT_ID_HWGC_START_AD_HI 0x4C
 257 #define CRT_ID_HWGC_START_AD_LO 0x4D
 258 #define CRT_ID_HWGC_DSTART_X    0x4E
 259 #define CRT_ID_HWGC_DSTART_Y    0x4F
 260 /* S3 extensions: System Extension Registers  */
 261 #define CRT_ID_EXT_SYS_CNTL_1   0x50
 262 #define CRT_ID_EXT_SYS_CNTL_2   0x51
 263 #define CRT_ID_EXT_BIOS_FLAG_1  0x52
 264 #define CRT_ID_EXT_MEM_CNTL_1   0x53
 265 #define CRT_ID_EXT_MEM_CNTL_2   0x54
 266 #define CRT_ID_EXT_DAC_CNTL     0x55
 267 #define CRT_ID_EX_SYNC_1        0x56
 268 #define CRT_ID_EX_SYNC_2        0x57
 269 #define CRT_ID_LAW_CNTL         0x58    /* LAW = Linear Address Window */
 270 #define CRT_ID_LAW_POS_HI       0x59
 271 #define CRT_ID_LAW_POS_LO       0x5A
 272 #define CRT_ID_GOUT_PORT        0x5C
 273 #define CRT_ID_EXT_HOR_OVF      0x5D
 274 #define CRT_ID_EXT_VER_OVF      0x5E
 275 #define CRT_ID_EXT_MEM_CNTL_3   0x60
 276 #define CRT_ID_EX_SYNC_3        0x63
 277 #define CRT_ID_EXT_MISC_CNTL    0x65
 278 #define CRT_ID_EXT_MISC_CNTL_1  0x66
 279 #define CRT_ID_EXT_MISC_CNTL_2  0x67
 280 #define CRT_ID_CONFIG_3         0x68
 281 #define CRT_ID_EXT_SYS_CNTL_3   0x69
 282 #define CRT_ID_EXT_SYS_CNTL_4   0x6A
 283 #define CRT_ID_EXT_BIOS_FLAG_3  0x6B
 284 #define CRT_ID_EXT_BIOS_FLAG_4  0x6C
 285
 286 /* Enhanced Commands Registers: */
 287 #define ECR_SUBSYSTEM_STAT      0x42E8
 288 #define ECR_SUBSYSTEM_CNTL      0x42E8
 289 #define ECR_ADV_FUNC_CNTL       0x4AE8
 290 #define ECR_CURRENT_Y_POS       0x82E8
 291 #define ECR_CURRENT_Y_POS2      0x82EA  /* Trio64 only */
 292 #define ECR_CURRENT_X_POS       0x86E8
 293 #define ECR_CURRENT_X_POS2      0x86EA  /* Trio64 only */
 294 #define ECR_DEST_Y__AX_STEP     0x8AE8
 295 #define ECR_DEST_Y2__AX_STEP2   0x8AEA  /* Trio64 only */
 296 #define ECR_DEST_X__DIA_STEP    0x8EE8
 297 #define ECR_DEST_X2__DIA_STEP2  0x8EEA  /* Trio64 only */
 298 #define ECR_ERR_TERM            0x92E8
 299 #define ECR_ERR_TERM2           0x92EA  /* Trio64 only */
 300 #define ECR_MAJ_AXIS_PIX_CNT    0x96E8
 301 #define ECR_MAJ_AXIS_PIX_CNT2   0x96EA  /* Trio64 only */
 302 #define ECR_GP_STAT             0x9AE8  /* GP = Graphics Processor */
 303 #define ECR_DRAW_CMD            0x9AE8
 304 #define ECR_DRAW_CMD2           0x9AEA  /* Trio64 only */
 305 #define ECR_SHORT_STROKE        0x9EE8
 306 #define ECR_BKGD_COLOR          0xA2E8  /* BKGD = Background */
 307 #define ECR_FRGD_COLOR          0xA6E8  /* FRGD = Foreground */
 308 #define ECR_BITPLANE_WRITE_MASK 0xAAE8
 309 #define ECR_BITPLANE_READ_MASK  0xAEE8
 310 #define ECR_COLOR_COMPARE       0xB2E8
 311 #define ECR_BKGD_MIX            0xB6E8
 312 #define ECR_FRGD_MIX            0xBAE8
 313 #define ECR_READ_REG_DATA       0xBEE8
 314 #define ECR_ID_MIN_AXIS_PIX_CNT 0x00
 315 #define ECR_ID_SCISSORS_TOP     0x01
 316 #define ECR_ID_SCISSORS_LEFT    0x02
 317 #define ECR_ID_SCISSORS_BUTTOM  0x03
 318 #define ECR_ID_SCISSORS_RIGHT   0x04
 319 #define ECR_ID_PIX_CNTL         0x0A
 320 #define ECR_ID_MULT_CNTL_MISC_2 0x0D
 321 #define ECR_ID_MULT_CNTL_MISC   0x0E
 322 #define ECR_ID_READ_SEL         0x0F
 323 #define ECR_PIX_TRANS           0xE2E8
 324 #define ECR_PIX_TRANS_EXT       0xE2EA
 325 #define ECR_PATTERN_Y           0xEAE8  /* Trio64 only */
 326 #define ECR_PATTERN_X           0xEAEA  /* Trio64 only */
 327
 328
 329 /* Pass-through */
 330 #define PASS_ADDRESS            0x40001
 331 #define PASS_ADDRESS_W          0x40001
 332
 333 /* Video DAC */
 334 #define VDAC_ADDRESS            0x03c8
 335 #define VDAC_ADDRESS_W          0x03c8
 336 #define VDAC_ADDRESS_R          0x03c7
 337 #define VDAC_STATE              0x03c7
 338 #define VDAC_DATA               0x03c9
 339 #define VDAC_MASK               0x03c6
 340
 341
 342 #define WGfx(ba, idx, val) \
 343         do { vgaw(ba, GCT_ADDRESS, idx); vgaw(ba, GCT_ADDRESS_W , val); } while (0)
 344
 345 #define WSeq(ba, idx, val) \
 346         do { vgaw(ba, SEQ_ADDRESS, idx); vgaw(ba, SEQ_ADDRESS_W , val); } while (0)
 347
 348 #define WCrt(ba, idx, val) \
 349         do { vgaw(ba, CRT_ADDRESS, idx); vgaw(ba, CRT_ADDRESS_W , val); } while (0)
 350
 351 #define WAttr(ba, idx, val) \
 352         do {    \
 353                 unsigned char tmp;\
 354                 tmp = vgar(ba, ACT_ADDRESS_RESET);\
 355                 vgaw(ba, ACT_ADDRESS_W, idx);\
 356                 vgaw(ba, ACT_ADDRESS_W, val);\
 357         } while (0)
 358
 359
 360 #define SetTextPlane(ba, m) \
 361         do { \
 362                 WGfx(ba, GCT_ID_READ_MAP_SELECT, m & 3 );\
 363                 WSeq(ba, SEQ_ID_MAP_MASK, (1 << (m & 3)));\
 364         } while (0)
 365
 366
 367 /* Gfx engine busy wait */
 368
 369 static inline void
 370 GfxBusyWait (ba)
 371         volatile void *ba;
 372 {
 373         int test;
 374
 375         do {
 376                 test = vgar16 (ba, ECR_GP_STAT);
 377                 __asm volatile ("nop");
 378         } while (test & (1 << 9));
 379 }
 380
 381
 382 static inline void
 383 GfxFifoWait(ba)
 384         volatile void *ba;
 385 {
 386         int test;
 387
 388         do {
 389                 test = vgar16 (ba, ECR_GP_STAT);
 390         } while (test & 0x0f);
 391 }
 392
 393
 394 /* Special wakeup/passthrough registers on graphics boards
 395  *
 396  * The methods have diverged a bit for each board, so
 397  * WPass(P) has been converted into a set of specific
 398  * inline functions.
 399  */
 400
 401 static inline unsigned char
 402 RAttr(ba, idx)
 403         volatile void *ba;
 404         short idx;
 405 {
 406
 407         vgaw(ba, ACT_ADDRESS_W, idx);
 408         delay(0);
 409         return vgar(ba, ACT_ADDRESS_R);
 410 }
 411
 412 static inline unsigned char
 413 RSeq(ba, idx)
 414         volatile void *ba;
 415         short idx;
 416 {
 417         vgaw(ba, SEQ_ADDRESS, idx);
 418         return vgar(ba, SEQ_ADDRESS_R);
 419 }
 420
 421 static inline unsigned char
 422 RCrt(ba, idx)
 423         volatile void *ba;
 424         short idx;
 425 {
 426         vgaw(ba, CRT_ADDRESS, idx);
 427         return vgar(ba, CRT_ADDRESS_R);
 428 }
 429
 430 static inline unsigned char
 431 RGfx(ba, idx)
 432         volatile void *ba;
 433         short idx;
 434 {
 435         vgaw(ba, GCT_ADDRESS, idx);
 436         return vgar(ba, GCT_ADDRESS_R);
 437 }
 438
 439 #endif /* _GRF_RHREG_H */