sys/arch/amiga/dev/if_esreg.h

   1 /*      $NetBSD: if_esreg.h,v 1.6 2003/01/28 22:35:05 wiz Exp $ */
   2
   3 /*
   4  * Copyright (c) 1995 Michael L. Hitch
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  17  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  18  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  19  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  20  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  21  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  22  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  23  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  24  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  25  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26  */
  27
  28 /*
  29  * SMC 91C90 register definitions
  30  */
  31
  32 union smcregs {
  33         struct {
  34                 volatile u_short tcr;   /* Transmit Control Register */
  35                 volatile u_short ephsr; /* EPH Status Register */
  36                 volatile u_short rcr;   /* Receive Control Register */
  37                 volatile u_short ecr;   /* Counter Register */
  38                 volatile u_short mir;   /* Memory Information Register */
  39                 volatile u_short mcr;   /* Memory Configuration Register */
  40                 volatile u_short resv;
  41                 volatile u_short bsr;   /* Bank Select Register */
  42         } b0;
  43         struct {
  44                 volatile u_short cr;    /* Configuration Register */
  45                 volatile u_short bar;   /* Base Address Register */
  46                 volatile u_short iar[3]; /* Individual Address Registers */
  47                 volatile u_short gpr;   /* General Purpose Register */
  48                 volatile u_short ctr;   /* Control Register */
  49                 volatile u_short bsr;   /* Bank Select Register */
  50         } b1;
  51         struct {
  52                 volatile u_short mmucr; /* MMU Command Register */
  53                 volatile u_char pnr;    /* Packet Number Register */
  54                 volatile u_char arr;    /* Allocation Result Register */
  55                 volatile u_short fifo;  /* FIFO Ports Register */
  56                 volatile u_short ptr;   /* Pointer Register */
  57                 volatile u_short data;  /* Data Register */
  58                 volatile u_short datax; /* Data Register (2nd mapping) */
  59                 volatile u_char ist;    /* Interrupt Status Register */
  60                 volatile u_char msk;    /* Interrupt Mask Register */
  61                 volatile u_short bsr;   /* Bank Select Register */
  62         } b2;
  63         struct {
  64                 volatile u_short mt[4]; /* Multicast Table */
  65                 volatile u_short resv[3];
  66                 volatile u_short bsr;   /* Bank Select Register */
  67         } b3;
  68 /*
  69  * Bank 2 registers defined as u_short fields
  70  */
  71         struct {
  72                 volatile u_short mmucr; /* MMU Command Register */
  73                 volatile u_short pnrarr;/* Packet Number/Allocation Result */
  74                 volatile u_short fifo;  /* FIFO Ports Register */
  75                 volatile u_short ptr;   /* Pointer Register */
  76                 volatile u_short data;  /* Data Register */
  77                 volatile u_short datax; /* Data Register (2nd mapping) */
  78                 volatile u_short istmsk;/* Interrupt Status/Mask Register */
  79                 volatile u_short bsr;   /* Bank Select Register */
  80         } w2;
  81 };
  82
  83 /* Transmit Control Register */
  84 #define TCR_PAD_EN      0x8000          /* Pad short frames */
  85 #define TCR_TXENA       0x0100          /* Transmit enabled */
  86 #define TCR_MON_CSN     0x0004          /* Monitor carrier */
  87
  88 /* EPH Status Register */
  89 #define EPHSR_16COL     0x1000          /* 16 collisions reached */
  90 #define EPHSR_MULCOL    0x0400          /* Multiple collsions */
  91 #define EPHSR_TX_SUC    0x0100          /* Last transmit successful */
  92 #define EPHSR_LOST_CAR  0x0004          /* Lost carrier */
  93
  94 /* Receive Control Register */
  95 #define RCR_ALLMUL      0x0400          /* Accept all Multicast frames */
  96 #define RCR_PRMS        0x0200          /* Promiscuous mode */
  97 #define RCR_EPH_RST     0x0080          /* Software activated Reset */
  98 #define RCR_FILT_CAR    0x0040          /* Filter carrier */
  99 #define RCR_STRIP_CRC   0x0002          /* Strip CRC */
 100 #define RCR_RXEN        0x0001          /* Receiver enabled */
 101
 102 /* Counter Register */
 103 #define ECR_MCC         0xf000          /* Multiple collision count */
 104 #define ECR_SCC         0x0f00          /* Single collision count */
 105 #define ECR_EDTX        0x00f0          /* Excess deferred TX count */
 106 #define ECR_DTX         0x000f          /* Deferred TX count */
 107
 108 /* Configuration Register */
 109 #define CR_RAM32K       0x2000          /* 32Kx16 RAM */
 110 #define CR_NO_WAIT_ST   0x0010          /* No wait state */
 111 #define CR_SET_SQLCH    0x0002          /* Squelch level 240mv */
 112
 113 /* Control Register */
 114 #define CTR_TE_ENA      0x2000          /* Transmit Error enable */
 115 #define CTR_AUTO_RLSE   0x0008          /* Auto Release */
 116
 117 /* MMU Command Register */
 118 #define MMUCR_NOOP      0x0000          /* No operation */
 119 #define MMUCR_ALLOC     0x2000          /* Allocate memory for TX */
 120 #define MMUCR_RESET     0x4000          /* Reset to intitial state */
 121 #define MMUCR_REM_RX    0x6000          /* Remove frame from top of RX FIFO */
 122 #define MMUCR_REMRLS_RX 0x8000          /* Remove & release from top of RX FIFO */
 123 #define MMUCR_RLSPKT    0xa000          /* Release specific packet */
 124 #define MMUCR_ENQ_TX    0xc000          /* Enqueue packet into TX FIFO */
 125 #define MMUCR_RESET_TX  0xe000          /* Reset TX FIFOs */
 126 #define MMUCR_BUSY      0x0100          /* MMU busy */
 127
 128 /* Allocation Result Register */
 129 #define ARR_FAILED      0x80            /* Allocation failed */
 130 #define ARR_APN         0x1f            /* Allocated packet number */
 131
 132 /* FIFO Ports Register */
 133 #define FIFO_TEMPTY     0x8000          /* TX queue empty */
 134 #define FIFO_TXPNR      0x1f00          /* TX done packet number */
 135 #define FIFO_REMPTY     0x0080          /* RX FIFO empty */
 136 #define FIFO_RXPNR      0x001f          /* RX FIFO packet number */
 137
 138 /* Pointer Register */
 139 #define PTR_RCV         0x0080          /* Use Receive area */
 140 #define PTR_AUTOINCR    0x0040          /* Auto increment pointer on access */
 141 #define PTR_READ        0x0020          /* Read access */
 142
 143 /* Interrupt Status Register */
 144 #define IST_EPHINT      0x20            /* EPH Interrupt */
 145 #define IST_RX_OVRN     0x10            /* RX Overrun */
 146 #define IST_ALLOC       0x08            /* MMU Allocation completed */
 147 #define IST_TX_EMPTY    0x04            /* TX FIFO empty */
 148 #define IST_TX          0x02            /* TX complete */
 149 #define IST_RX          0x01            /* RX complete */
 150
 151 /* Interrupt Acknowlege Register */
 152 #define ACK_RX_OVRN     IST_RX_OVRN
 153 #define ACK_TX_EMPTY    IST_TX_EMPTY
 154 #define ACK_TX          IST_TX
 155
 156 /* Interrupt Mask Register */
 157 #define MSK_EPHINT      0x20            /* EPH Interrupt */
 158 #define MSK_RX_OVRN     0x10            /* RX Overrun */
 159 #define MSK_ALLOC       0x08            /* MMU Allocation completed */
 160 #define MSK_TX_EMPTY    0x04            /* TX FIFO empty */
 161 #define MSK_TX          0x02            /* TX complete */
 162 #define MSK_RX          0x01            /* RX complete */
 163
 164 /* Bank Select Register */
 165 #define BSR_MASK        0x0300
 166 #define BSR_BANK0       0x0000          /* Select bank 0 */
 167 #define BSR_BANK1       0x0100          /* Select bank 1 */
 168 #define BSR_BANK2       0x0200          /* Select bank 2 */
 169 #define BSR_BANK3       0x0300          /* Select bank 3 */
 170
 171 /* Packet Receive Frame Status Word */
 172 #define RFSW_ALGNERR    0x8000          /* Alignment Error */
 173 #define RFSW_BRDCST     0x4000          /* Broadcast frame */
 174 #define RFSW_BADCRC     0x2000          /* Bad CRC */
 175 #define RFSW_ODDFRM     0x1000          /* Odd number of bytes in frame */
 176 #define RFSW_TOOLNG     0x0800          /* Frame was too long */
 177 #define RFSW_TOOSHORT   0x0400          /* Frame was too short */
 178 #define RFSW_HASH       0x007e          /* Multicast hash value */
 179 #define RFSW_MULTCAST   0x0001          /* Multicast frame */
 180
 181 /* Control byte */
 182 #define CTLB_ODD        0x20            /* Odd number of bytes in frame */
 183 #define CTLB_CRC        0x10            /* Append CRC to transmitted frame */