sys/arch/amiga/dev/scireg.h

   1 /*      $NetBSD: scireg.h,v 1.4.2.3 2004/09/21 13:12:31 skrll Exp $     */
   2
   3 /*
   4  * Copyright (c) 1990 The Regents of the University of California.
   5  * All rights reserved.
   6  *
   7  * This code is derived from software contributed to Berkeley by
   8  * Van Jacobson of Lawrence Berkeley Laboratory.
   9  *
  10  * Redistribution and use in source and binary forms, with or without
  11  * modification, are permitted provided that the following conditions
  12  * are met:
  13  * 1. Redistributions of source code must retain the above copyright
  14  *    notice, this list of conditions and the following disclaimer.
  15  * 2. Redistributions in binary form must reproduce the above copyright
  16  *    notice, this list of conditions and the following disclaimer in the
  17  *    documentation and/or other materials provided with the distribution.
  18  * 3. Neither the name of the University nor the names of its contributors
  19  *    may be used to endorse or promote products derived from this software
  20  *    without specific prior written permission.
  21  *
  22  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
  23  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  24  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  25  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  26  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  27  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  28  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  29  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  30  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  31  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  32  * SUCH DAMAGE.
  33  *
  34  *      @(#)scireg.h    7.3 (Berkeley) 2/5/91
  35  */
  36
  37 /*
  38  * NCR 5380 SCSI interface hardware description.
  39  *
  40  */
  41
  42 #if 0   /* for reference */
  43 typedef struct {
  44         unsigned char pad0[1];
  45         volatile unsigned char sci_data;        /* r:  Current data */
  46 #define sci_odata sci_data                      /* w:  Out data */
  47
  48         unsigned char pad1[1];
  49         volatile unsigned char sci_icmd;        /* rw: Initiator command */
  50
  51         unsigned char pad2[1];
  52         volatile unsigned char sci_mode;        /* rw: Mode */
  53
  54         unsigned char pad3[1];
  55         volatile unsigned char sci_tcmd;        /* rw: Target command */
  56
  57         unsigned char pad4[1];
  58         volatile unsigned char sci_bus_csr;     /* r:  Bus Status */
  59 #define sci_sel_enb sci_bus_csr                 /* w:  Select enable */
  60
  61         unsigned char pad5[1];
  62         volatile unsigned char sci_csr;         /* r:  Status */
  63 #define sci_dma_send sci_csr                    /* w:  Start DMA send data */
  64
  65         unsigned char pad6[1];
  66         volatile unsigned char sci_idata;       /* r:  Input data */
  67 #define sci_trecv sci_idata                     /* w:  Start DMA receive, target */
  68
  69         unsigned char pad7[1];
  70         volatile unsigned char sci_iack;        /* r:  Interrupt Acknowledge  */
  71 #define sci_irecv sci_iack                      /* w:  Start DMA receive, initiator */
  72 } sci_regmap_t;
  73 #endif
  74
  75 /*
  76  * Initiator command register
  77  */
  78
  79 #define SCI_ICMD_DATA           0x01            /* rw: Assert data bus   */
  80 #define SCI_ICMD_ATN            0x02            /* rw: Assert ATN signal */
  81 #define SCI_ICMD_SEL            0x04            /* rw: Assert SEL signal */
  82 #define SCI_ICMD_BSY            0x08            /* rw: Assert BSY signal */
  83 #define SCI_ICMD_ACK            0x10            /* rw: Assert ACK signal */
  84 #define SCI_ICMD_LST            0x20            /* r:  Lost arbitration */
  85 #define SCI_ICMD_DIFF   SCI_ICMD_LST            /* w:  Differential cable */
  86 #define SCI_ICMD_AIP            0x40            /* r:  Arbitration in progress */
  87 #define SCI_ICMD_TEST   SCI_ICMD_AIP            /* w:  Test mode */
  88 #define SCI_ICMD_RST            0x80            /* rw: Assert RST signal */
  89
  90
  91 /*
  92  * Mode register
  93  */
  94
  95 #define SCI_MODE_ARB            0x01            /* rw: Start arbitration */
  96 #define SCI_MODE_DMA            0x02            /* rw: Enable DMA xfers */
  97 #define SCI_MODE_MONBSY         0x04            /* rw: Monitor BSY signal */
  98 #define SCI_MODE_DMA_IE         0x08            /* rw: Enable DMA complete interrupt */
  99 #define SCI_MODE_PERR_IE        0x10            /* rw: Interrupt on parity errors */
 100 #define SCI_MODE_PAR_CHK        0x20            /* rw: Check parity */
 101 #define SCI_MODE_TARGET         0x40            /* rw: Target mode (Initiator if 0) */
 102 #define SCI_MODE_BLOCKDMA       0x80            /* rw: Block-mode DMA handshake (MBZ) */
 103
 104
 105 /*
 106  * Target command register
 107  */
 108
 109 #define SCI_TCMD_IO             0x01            /* rw: Assert I/O signal */
 110 #define SCI_TCMD_CD             0x02            /* rw: Assert C/D signal */
 111 #define SCI_TCMD_MSG            0x04            /* rw: Assert MSG signal */
 112 #define SCI_TCMD_PHASE_MASK     0x07            /* r:  Mask for current bus phase */
 113 #define SCI_TCMD_REQ            0x08            /* rw: Assert REQ signal */
 114 #define SCI_TCMD_LAST_SENT      0x80            /* ro: Last byte was xferred
 115                                                  *     (not on 5380/1) */
 116
 117 #define SCI_PHASE(x)            ((x>>2) & 7)
 118
 119 /*
 120  * Current (SCSI) Bus status
 121  */
 122
 123 #define SCI_BUS_DBP             0x01            /* r:  Data Bus parity */
 124 #define SCI_BUS_SEL             0x02            /* r:  SEL signal */
 125 #define SCI_BUS_IO              0x04            /* r:  I/O signal */
 126 #define SCI_BUS_CD              0x08            /* r:  C/D signal */
 127 #define SCI_BUS_MSG             0x10            /* r:  MSG signal */
 128 #define SCI_BUS_REQ             0x20            /* r:  REQ signal */
 129 #define SCI_BUS_BSY             0x40            /* r:  BSY signal */
 130 #define SCI_BUS_RST             0x80            /* r:  RST signal */
 131
 132 #define SCI_CUR_PHASE(x)        SCSI_PHASE((x)>>2)
 133
 134 /*
 135  * Bus and Status register
 136  */
 137
 138 #define SCI_CSR_ACK             0x01            /* r:  ACK signal */
 139 #define SCI_CSR_ATN             0x02            /* r:  ATN signal */
 140 #define SCI_CSR_DISC            0x04            /* r:  Disconnected (BSY==0) */
 141 #define SCI_CSR_PHASE_MATCH     0x08            /* r:  Bus and SCI_TCMD match */
 142 #define SCI_CSR_INT             0x10            /* r:  Interrupt request */
 143 #define SCI_CSR_PERR            0x20            /* r:  Parity error */
 144 #define SCI_CSR_DREQ            0x40            /* r:  DMA request */
 145 #define SCI_CSR_DONE            0x80            /* r:  DMA count is zero */
 146