sys/arch/amiga/dev/siopreg.h

   1 /*      $NetBSD: siopreg.h,v 1.13 2005/12/11 12:16:28 christos Exp $    */
   2
   3 /*
   4  * Copyright (c) 1990 The Regents of the University of California.
   5  * All rights reserved.
   6  *
   7  * This code is derived from software contributed to Berkeley by
   8  * Van Jacobson of Lawrence Berkeley Laboratory.
   9  *
  10  * Redistribution and use in source and binary forms, with or without
  11  * modification, are permitted provided that the following conditions
  12  * are met:
  13  * 1. Redistributions of source code must retain the above copyright
  14  *    notice, this list of conditions and the following disclaimer.
  15  * 2. Redistributions in binary form must reproduce the above copyright
  16  *    notice, this list of conditions and the following disclaimer in the
  17  *    documentation and/or other materials provided with the distribution.
  18  * 3. Neither the name of the University nor the names of its contributors
  19  *    may be used to endorse or promote products derived from this software
  20  *    without specific prior written permission.
  21  *
  22  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
  23  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  24  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  25  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  26  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  27  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  28  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  29  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  30  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  31  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  32  * SUCH DAMAGE.
  33  *
  34  *      @(#)siopreg.h   7.3 (Berkeley) 2/5/91
  35  */
  36
  37 /*
  38  * NCR 53C710 SCSI interface hardware description.
  39  *
  40  * From the Mach scsi driver for the 53C700
  41  */
  42
  43 typedef struct {
  44
  45 #ifndef ARCH_720
  46
  47 /*00*/  volatile unsigned char  siop_sien;      /* rw: SCSI Interrupt Enable */
  48 /*01*/  volatile unsigned char  siop_sdid;      /* rw: SCSI Destination ID */
  49 /*02*/  volatile unsigned char  siop_scntl1;    /* rw: SCSI control reg 1 */
  50 /*03*/  volatile unsigned char  siop_scntl0;    /* rw: SCSI control reg 0 */
  51
  52 /*04*/  volatile unsigned char  siop_socl;      /* rw: SCSI Output Control Latch */
  53 /*05*/  volatile unsigned char  siop_sodl;      /* rw: SCSI Output Data Latch */
  54 /*06*/  volatile unsigned char  siop_sxfer;     /* rw: SCSI Transfer reg */
  55 /*07*/  volatile unsigned char  siop_scid;      /* rw: SCSI Chip ID reg */
  56
  57 /*08*/  volatile unsigned char  siop_sbcl;      /* ro: SCSI Bus Control Lines */
  58 /*09*/  volatile unsigned char  siop_sbdl;      /* ro: SCSI Bus Data Lines */
  59 /*0a*/  volatile unsigned char  siop_sidl;      /* ro: SCSI Input Data Latch */
  60 /*0b*/  volatile unsigned char  siop_sfbr;      /* ro: SCSI First Byte Received */
  61
  62 /*0c*/  volatile unsigned char  siop_sstat2;    /* ro: SCSI status reg 2 */
  63 /*0d*/  volatile unsigned char  siop_sstat1;    /* ro: SCSI status reg 1 */
  64 /*0e*/  volatile unsigned char  siop_sstat0;    /* ro: SCSI status reg 0 */
  65 /*0f*/  volatile unsigned char  siop_dstat;     /* ro: DMA status */
  66
  67 /*10*/  volatile unsigned long  siop_dsa;       /* rw: Data Structure Address */
  68
  69 /*14*/  volatile unsigned char  siop_ctest3;    /* ro: Chip test register 3 */
  70 /*15*/  volatile unsigned char  siop_ctest2;    /* ro: Chip test register 2 */
  71 /*16*/  volatile unsigned char  siop_ctest1;    /* ro: Chip test register 1 */
  72 /*17*/  volatile unsigned char  siop_ctest0;    /* ro: Chip test register 0 */
  73
  74 /*18*/  volatile unsigned char  siop_ctest7;    /* rw: Chip test register 7 */
  75 /*19*/  volatile unsigned char  siop_ctest6;    /* rw: Chip test register 6 */
  76 /*1a*/  volatile unsigned char  siop_ctest5;    /* rw: Chip test register 5 */
  77 /*1b*/  volatile unsigned char  siop_ctest4;    /* rw: Chip test register 4 */
  78
  79 /*1c*/  volatile unsigned long  siop_temp;      /* rw: Temporary Stack reg */
  80
  81 /*20*/  volatile unsigned char  siop_lcrc;      /* rw: LCRC value */
  82 /*21*/  volatile unsigned char  siop_ctest8;    /* rw: Chip test register 8 */
  83 /*22*/  volatile unsigned char  siop_istat;     /* rw: Interrupt Status reg */
  84 /*23*/  volatile unsigned char  siop_dfifo;     /* rw: DMA FIFO */
  85
  86 /*24*/  volatile unsigned char  siop_dcmd;      /* rw: DMA Command Register */
  87 /*25*/  volatile unsigned char  siop_dbc2;      /* rw: DMA Byte Counter reg */
  88 /*26*/  volatile unsigned char  siop_dbc1;
  89 /*27*/  volatile unsigned char  siop_dbc0;
  90
  91 /*28*/  volatile unsigned long  siop_dnad;      /* rw: DMA Next Address */
  92
  93 /*2c*/  volatile unsigned long  siop_dsp;       /* rw: DMA SCRIPTS Pointer reg */
  94
  95 /*30*/  volatile unsigned long  siop_dsps;      /* rw: DMA SCRIPTS Pointer Save reg */
  96
  97 /*34*/  volatile unsigned long  siop_scratch;   /* rw: Scratch Register */
  98
  99 /*38*/  volatile unsigned char  siop_dcntl;     /* rw: DMA Control reg */
 100 /*39*/  volatile unsigned char  siop_dwt;       /* rw: DMA Watchdog Timer */
 101 /*3a*/  volatile unsigned char  siop_dien;      /* rw: DMA Interrupt Enable */
 102 /*3b*/  volatile unsigned char  siop_dmode;     /* rw: DMA Mode reg */
 103
 104 /*3c*/  volatile unsigned long  siop_adder;
 105
 106 #else
 107
 108 /*00*/  volatile unsigned char  siop_scntl3;    /* rw: SCSI control reg 3 */
 109 /*01*/  volatile unsigned char  siop_scntl2;    /* rw: SCSI control reg 2 */
 110 /*02*/  volatile unsigned char  siop_scntl1;    /* rw: SCSI control reg 1 */
 111 /*03*/  volatile unsigned char  siop_scntl0;    /* rw: SCSI control reg 0 */
 112
 113 /*04*/  volatile unsigned char  siop_gpreg;     /* rw: SCSI  */
 114 /*05*/  volatile unsigned char  siop_sdid;      /* rw: SCSI Destination ID */
 115 /*06*/  volatile unsigned char  siop_sxfer;     /* rw: SCSI Transfer reg */
 116 /*07*/  volatile unsigned char  siop_scid;      /* rw: SCSI Chip ID reg */
 117
 118 /*08*/  volatile unsigned char  siop_sbcl;      /* ro: SCSI Bus Control Lines */
 119 /*09*/  volatile unsigned char  siop_ssid;      /* ro: SCSI */
 120 /*0a*/  volatile unsigned char  siop_socl;      /* rw: SCSI Output Control Latch */
 121 /*0b*/  volatile unsigned char  siop_sfbr;      /* ro: SCSI First Byte Received */
 122
 123 /*0c*/  volatile unsigned char  siop_sstat2;    /* ro: SCSI status reg 2 */
 124 /*0d*/  volatile unsigned char  siop_sstat1;    /* ro: SCSI status reg 1 */
 125 /*0e*/  volatile unsigned char  siop_sstat0;    /* ro: SCSI status reg 0 */
 126 /*0f*/  volatile unsigned char  siop_dstat;     /* ro: DMA status */
 127
 128 /*10*/  volatile unsigned long  siop_dsa;       /* rw: Data Structure Address */
 129
 130 /*14*/  volatile unsigned char  siop_14_;       /* ??: */
 131 /*15*/  volatile unsigned char  siop_15_;       /* ??: */
 132 /*16*/  volatile unsigned char  siop_16_;       /* ??: */
 133 /*17*/  volatile unsigned char  siop_istat;     /* rw: Interrupt Status reg */
 134
 135 /*18*/  volatile unsigned char  siop_ctest3;    /* ro: Chip test register 3 */
 136 /*19*/  volatile unsigned char  siop_ctest2;    /* ro: Chip test register 2 */
 137 /*1a*/  volatile unsigned char  siop_ctest1;    /* ro: Chip test register 1 */
 138 /*1b*/  volatile unsigned char  siop_ctest0;    /* ro: Chip test register 0 */
 139
 140 /*1c*/  volatile unsigned long  siop_temp;      /* rw: Temporary Stack reg */
 141
 142 /*20*/  volatile unsigned char  siop_ctest6;    /* rw: Chip test register 6 */
 143 /*21*/  volatile unsigned char  siop_ctest5;    /* rw: Chip test register 5 */
 144 /*22*/  volatile unsigned char  siop_ctest4;    /* rw: Chip test register 4 */
 145 /*23*/  volatile unsigned char  siop_dfifo;     /* rw: DMA FIFO */
 146
 147 /*24*/  volatile unsigned char  siop_dcmd;      /* rw: DMA Command Register */
 148 /*25*/  volatile unsigned char  siop_dbc2;      /* rw: DMA Byte Counter reg */
 149 /*26*/  volatile unsigned char  siop_dbc1;
 150 /*27*/  volatile unsigned char  siop_dbc0;
 151
 152 /*28*/  volatile unsigned long  siop_dnad;      /* rw: DMA Next Address */
 153
 154 /*2c*/  volatile unsigned long  siop_dsp;       /* rw: DMA SCRIPTS Pointer reg */
 155
 156 /*30*/  volatile unsigned long  siop_dsps;      /* rw: DMA SCRIPTS Pointer Save reg */
 157
 158 /*34*/  volatile unsigned long  siop_scratcha;  /* rw: Scratch Register A */
 159
 160 /*38*/  volatile unsigned char  siop_dcntl;     /* rw: DMA Control reg */
 161 /*39*/  volatile unsigned char  siop_dwt;       /* rw: DMA Watchdog Timer */
 162 /*3a*/  volatile unsigned char  siop_dien;      /* rw: DMA Interrupt Enable */
 163 /*3b*/  volatile unsigned char  siop_dmode;     /* rw: DMA Mode reg */
 164
 165 /*3c*/  volatile unsigned long  siop_adder;
 166
 167 /*40*/  volatile unsigned short siop_sist;      /* rw: SCSI Interrupt Status */
 168         #define SIOP_SIST_STO   0x0400          /*     timeout (select) */
 169         #define SIOP_SIST_GEN   0x0200          /*     timeout (general) */
 170         #define SIOP_SIST_HTH   0x0100          /*     handshake timer expired */
 171         #define SIOP_SIST_MA    0x0080          /*     phase mismatch */
 172         #define SIOP_SIST_CMP   0x0040          /*     function complete */
 173         #define SIOP_SIST_SEL   0x0020          /*     selected */
 174         #define SIOP_SIST_RSL   0x0010          /*     reselected */
 175         #define SIOP_SIST_SGE   0x0008          /*     gross error (over/underflow) */
 176         #define SIOP_SIST_UDC   0x0004          /*     unexpected disconnect */
 177         #define SIOP_SIST_RST   0x0002          /*     RST received */
 178         #define SIOP_SIST_PAR   0x0001          /*     scsi parity error */
 179 /*42*/  volatile unsigned short siop_sien;      /* rw: SCSI Interrupt Enable */
 180         #define SIOP_SIEN_STO   0x0400          /*     timeout (select) */
 181         #define SIOP_SIEN_GEN   0x0200          /*     timeout (general) */
 182         #define SIOP_SIEN_HTH   0x0100          /*     handshake timer expired */
 183         #define SIOP_SIEN_MA    0x0080          /*     phase mispatch */
 184         #define SIOP_SIEN_CMP   0x0040          /*     function complete */
 185         #define SIOP_SIEN_SEL   0x0020          /*     selected */
 186         #define SIOP_SIEN_RSL   0x0010          /*     reselected */
 187         #define SIOP_SIEN_SGE   0x0008          /*     gross error (over/underflow) */
 188         #define SIOP_SIEN_UDC   0x0004          /*     unexpected disconnect */
 189         #define SIOP_SIEN_RST   0x0002          /*     scsi bus reset */
 190         #define SIOP_SIEN_PAR   0x0001          /*     scsi parity error */
 191
 192 /*44*/  volatile unsigned char  siop_gpcntl;    /* rw: SCSI  */
 193 /*45*/  volatile unsigned char  siop_macntl;    /* rw: SCSI  */
 194 /*46*/  volatile unsigned char  siop_swide;     /* rw: SCSI  */
 195 /*47*/  volatile unsigned char  siop_slpar;     /* rw: SCSI  */
 196
 197 /*48*/  volatile unsigned short siop_respid;    /* rw: SCSI Reselect-IDS */
 198 /*4a*/  volatile unsigned char  siop_stime1;    /* rw: SCSI  */
 199 /*4b*/  volatile unsigned char  siop_stime0;    /* rw: SCSI  */
 200
 201 /*4c*/  volatile unsigned char  siop_stest3;    /* ro: Chip test register 3 */
 202 #define SIOP_STEST3_HSC         0x20    /* Halt SCSI Clock */
 203 /*4d*/  volatile unsigned char  siop_stest2;    /* ro: Chip test register 2 */
 204 /*4e*/  volatile unsigned char  siop_stest1;    /* ro: Chip test register 1 */
 205 #define SIOP_STEST1_DBLEN       0x08    /* SCLK Double Enable */
 206 #define SIOP_STEST1_DBLSEL      0x04    /* SCLK Doubler Select */
 207 /*4f*/  volatile unsigned char  siop_stest0;    /* ro: Chip test register 0 */
 208
 209 /*50*/  volatile unsigned char  siop_50_;       /* rw: SCSI  */
 210 /*51*/  volatile unsigned char  siop_stest4;    /* rw: SCSI  */
 211 /*52*/  volatile unsigned short siop_sidl;      /* ro: SCSI Input Data Latch */
 212
 213 /*54*/  volatile unsigned short siop_54_;       /* rw: SCSI  */
 214 /*56*/  volatile unsigned short siop_sodl;      /* rw: SCSI Output Data Latch */
 215
 216 /*58*/  volatile unsigned short siop_58_;       /* rw: SCSI  */
 217 /*5a*/  volatile unsigned short siop_sbdl;      /* ro: SCSI Bus Data Lines */
 218
 219 /*5c*/  volatile unsigned long  siop_scratchb;  /* rw: Scratch Register B */
 220 #endif
 221
 222 } siop_regmap_t;
 223 typedef volatile siop_regmap_t *siop_regmap_p;
 224
 225 /*
 226  * Register defines
 227  */
 228
 229 /* Scsi control register 0 (scntl0) */
 230
 231 #define SIOP_SCNTL0_ARB         0xc0    /* Arbitration mode */
 232 #       define  SIOP_ARB_SIMPLE 0x00
 233 #       define  SIOP_ARB_FULL   0xc0
 234 #define SIOP_SCNTL0_START       0x20    /* Start Sequence */
 235 #define SIOP_SCNTL0_WATN        0x10    /* (Select) With ATN */
 236 #define SIOP_SCNTL0_EPC         0x08    /* Enable Parity Checking */
 237 #define SIOP_SCNTL0_EPG         0x04    /* Enable Parity Generation */
 238 #define SIOP_SCNTL0_AAP         0x02    /* Assert ATN on Parity Error */
 239 #define SIOP_SCNTL0_TRG         0x01    /* Target Mode */
 240
 241 /* Scsi control register 1 (scntl1) */
 242
 243 #define SIOP_SCNTL1_EXC         0x80    /* Extra Clock Cycle of data setup */
 244 #define SIOP_SCNTL1_ADB         0x40    /* Assert Data Bus */
 245 #ifndef ARCH_720
 246 #define SIOP_SCNTL1_ESR         0x20    /* Enable Selection/Reselection */
 247 #else
 248 #define SIOP_SCNTL1_DHP         0x20    /* Disable Halt on Parity or ATN */
 249 #endif
 250 #define SIOP_SCNTL1_CON         0x10    /* Connected */
 251 #define SIOP_SCNTL1_RST         0x08    /* Assert RST */
 252 #define SIOP_SCNTL1_AESP        0x04    /* Assert even SCSI parity */
 253 #ifndef ARCH_720
 254 #define SIOP_SCNTL1_RES0        0x02    /* Reserved */
 255 #define SIOP_SCNTL1_RES1        0x01    /* Reserved */
 256 #else
 257 #define SIOP_SCNTL1_IARB        0x02    /* Immediate Arbitration */
 258 #define SIOP_SCNTL1_SST         0x01    /* Start SCSI Transfer */
 259 #endif
 260
 261 /* Scsi control register 3 (scntl3) */
 262
 263 #ifdef ARCH_720
 264 #define SIOP_SCNTL3_ULTRA       0x80    /* Ultra Enable */
 265 #define SIOP_SCNTL3_SCF         0x70    /* Synch Clock Conversion Factor */
 266 #define SIOP_SCNTL3_EWS         0x08    /* Enable Wide SCSI */
 267 #define SIOP_SCNTL3_CCF         0x07    /* Clock Conversion Factor */
 268 #endif
 269
 270 /* Scsi interrupt enable register (sien) */
 271
 272 #ifndef ARCH_720
 273 #define SIOP_SIEN_M_A           0x80    /* Phase Mismatch or ATN active */
 274 #define SIOP_SIEN_FCMP          0x40    /* Function Complete */
 275 #define SIOP_SIEN_STO           0x20    /* (Re)Selection timeout */
 276 #define SIOP_SIEN_SEL           0x10    /* (Re)Selected */
 277 #define SIOP_SIEN_SGE           0x08    /* SCSI Gross Error */
 278 #define SIOP_SIEN_UDC           0x04    /* Unexpected Disconnect */
 279 #define SIOP_SIEN_RST           0x02    /* RST asserted */
 280 #define SIOP_SIEN_PAR           0x01    /* Parity Error */
 281 #endif
 282
 283 /* Scsi chip ID (scid) */
 284
 285 #define SIOP_SCID_VALUE(i)      (1<<i)
 286 #ifdef ARCH_720
 287 #define SIOP_SCID_RRE           0x40    /* Enable Response to Reselection */
 288 #define SIOP_SCID_SRE           0x20    /* Enable Response to Selection */
 289 #endif
 290
 291 /* Scsi transfer register (sxfer) */
 292
 293 #ifndef ARCH_720
 294 #define SIOP_SXFER_DHP          0x80    /* Disable Halt on Parity error/ ATN asserted */
 295 #define SIOP_SXFER_TP           0x70    /* Synch Transfer Period */
 296                                         /* see specs for formulas:
 297                                                 Period = TCP * (4 + XFERP )
 298                                                 TCP = 1 + CLK + 1..2;
 299                                          */
 300 #define SIOP_SXFER_MO           0x0f    /* Synch Max Offset */
 301 #       define  SIOP_MAX_OFFSET 8
 302 #else
 303 #define SIOP_SXFER_TP           0xe0    /* Synch Transfer Period */
 304                                         /* see specs for formulas:
 305                                                 Period = TCP * (4 + XFERP )
 306                                                 TCP = 1 + CLK + 1..2;
 307                                          */
 308 #define SIOP_SXFER_MO           0x1f    /* Synch Max Offset */
 309 #       define  SIOP_MAX_OFFSET 16
 310 #endif
 311
 312 /* Scsi output data latch register (sodl) */
 313
 314 /* Scsi output control latch register (socl) */
 315
 316 #define SIOP_REQ                0x80    /* SCSI signal <x> asserted */
 317 #define SIOP_ACK                0x40
 318 #define SIOP_BSY                0x20
 319 #define SIOP_SEL                0x10
 320 #define SIOP_ATN                0x08
 321 #define SIOP_MSG                0x04
 322 #define SIOP_CD                 0x02
 323 #define SIOP_IO                 0x01
 324
 325 #define SIOP_PHASE(socl)        SCSI_PHASE(socl)
 326
 327 /* Scsi first byte received register (sfbr) */
 328
 329 /* Scsi input data latch register (sidl) */
 330
 331 /* Scsi bus data lines register (sbdl) */
 332
 333 /* Scsi bus control lines register (sbcl).  Same as socl */
 334
 335 /* DMA status register (dstat) */
 336
 337 #define SIOP_DSTAT_DFE          0x80    /* DMA FIFO empty */
 338 #ifndef ARCH_720
 339 #define SIOP_DSTAT_RES          0x40
 340 #else
 341 #define SIOP_DSTAT_HPE          0x40    /* Host Parity Error */
 342 #endif
 343 #define SIOP_DSTAT_BF           0x20    /* Bus fault */
 344 #define SIOP_DSTAT_ABRT         0x10    /* Aborted */
 345 #define SIOP_DSTAT_SSI          0x08    /* SCRIPT Single Step */
 346 #define SIOP_DSTAT_SIR          0x04    /* SCRIPT Interrupt Instruction */
 347 #define SIOP_DSTAT_WTD          0x02    /* Watchdog Timeout Detected */
 348 #define SIOP_DSTAT_IID          0x01    /* Invalid Instruction Detected */
 349
 350 /* Scsi status register 0 (sstat0) */
 351
 352 #ifndef ARCH_720
 353 #define SIOP_SSTAT0_M_A         0x80    /* Phase Mismatch or ATN active */
 354 #define SIOP_SSTAT0_FCMP        0x40    /* Function Complete */
 355 #define SIOP_SSTAT0_STO         0x20    /* (Re)Selection timeout */
 356 #define SIOP_SSTAT0_SEL         0x10    /* (Re)Selected */
 357 #define SIOP_SSTAT0_SGE         0x08    /* SCSI Gross Error */
 358 #define SIOP_SSTAT0_UDC         0x04    /* Unexpected Disconnect */
 359 #define SIOP_SSTAT0_RST         0x02    /* RST asserted */
 360 #define SIOP_SSTAT0_PAR         0x01    /* Parity Error */
 361 #else
 362 #define SIOP_SSTAT0_ILF         0x80    /* SIDL lsb full */
 363 #define SIOP_SSTAT0_ORF         0x40    /* SODR lsb full */
 364 #define SIOP_SSTAT0_OLF         0x20    /* SODL lsb full */
 365 #define SIOP_SSTAT0_AIP         0x10    /* Arbitration in progress */
 366 #define SIOP_SSTAT0_LOA         0x08    /* Lost Arbitration */
 367 #define SIOP_SSTAT0_WOA         0x04    /* Won Arbitration */
 368 #define SIOP_SSTAT0_RST         0x02    /* SCSI RST/ signal */
 369 #define SIOP_SSTAT0_SDP0        0x01    /* SCSI SDP0/ parity signal */
 370 #endif
 371
 372 /* Scsi status register 1 (sstat1) */
 373
 374 #ifndef ARCH_720
 375 #define SIOP_SSTAT1_ILF         0x80    /* Input latch (sidl) full */
 376 #define SIOP_SSTAT1_ORF         0x40    /* output reg (sodr) full */
 377 #define SIOP_SSTAT1_OLF         0x20    /* output latch (sodl) full */
 378 #define SIOP_SSTAT1_AIP         0x10    /* Arbitration in progress */
 379 #define SIOP_SSTAT1_LOA         0x08    /* Lost arbitration */
 380 #define SIOP_SSTAT1_WOA         0x04    /* Won arbitration */
 381 #define SIOP_SSTAT1_RST         0x02    /* SCSI RST current value */
 382 #define SIOP_SSTAT1_SDP         0x01    /* SCSI SDP current value */
 383 #else
 384 #define SIOP_SSTAT1_FF          0xf0    /* SCSI FIFO flags (bytecount) */
 385 #define SIOP_SSTAT1_SDP0        0x08    /* Latched (on REQ) SCSI Parity */
 386 #define SIOP_SSTAT1_MSG         0x04    /* Latched SCSI phase */
 387 #define SIOP_SSTAT1_CD          0x02
 388 #define SIOP_SSTAT1_IO          0x01
 389 #endif
 390
 391 /* Scsi status register 2 (sstat2) */
 392
 393 #ifndef ARCH_720
 394 #define SIOP_SSTAT2_FF          0xf0    /* SCSI FIFO flags (bytecount) */
 395 #       define SIOP_SCSI_FIFO_DEEP      8
 396 #define SIOP_SSTAT2_SDP         0x08    /* Latched (on REQ) SCSI SDP */
 397 #define SIOP_SSTAT2_MSG         0x04    /* Latched SCSI phase */
 398 #define SIOP_SSTAT2_CD          0x02
 399 #define SIOP_SSTAT2_IO          0x01
 400 #else
 401 #define SIOP_SSTAT2_ILF1        0x80    /* SIDL msb full */
 402 #define SIOP_SSTAT2_ORF1        0x40    /* SODR msb full */
 403 #define SIOP_SSTAT2_OLF1        0x20    /* SODL msb full */
 404 #define SIOP_SSTAT2_FF4         0x10    /* FIFO flags bit 4 */
 405 #define SIOP_SSTAT2_SPL1        0x08    /* Latched Parity for SD15-8 */
 406 #define SIOP_SSTAT2_DIFF        0x04    /* DIFFSENSE Sense */
 407 #define SIOP_SSTAT2_LDSC        0x02    /* Last Disconnect */
 408 #define SIOP_SSTAT2_SDP1        0x01    /* SCSI SDP1 Parity */
 409 #endif
 410
 411 /* Chip test register 0 (ctest0) */
 412
 413 #ifndef ARCH_720
 414 #define SIOP_CTEST0_RES0        0x80
 415 #define SIOP_CTEST0_BTD         0x40    /* Byte-to-byte Timer Disable */
 416 #define SIOP_CTEST0_GRP         0x20    /* Generate Receive Parity for Passthrough */
 417 #define SIOP_CTEST0_EAN         0x10    /* Enable Active Negation */
 418 #define SIOP_CTEST0_HSC         0x08    /* Halt SCSI clock */
 419 #define SIOP_CTEST0_ERF         0x04    /* Extend REQ/ACK Filtering */
 420 #define SIOP_CTEST0_RES1        0x02
 421 #define SIOP_CTEST0_DDIR        0x01    /* Xfer direction (1-> from SCSI bus) */
 422 #endif
 423
 424 /* Chip test register 1 (ctest1) */
 425
 426 #define SIOP_CTEST1_FMT         0xf0    /* Byte empty in DMA FIFO bottom (high->byte3) */
 427 #define SIOP_CTEST1_FFL         0x0f    /* Byte full in DMA FIFO top, same */
 428
 429 /* Chip test register 2 (ctest2) */
 430
 431 #ifndef ARCH_720
 432 #define SIOP_CTEST2_RES         0x80
 433 #else
 434 #define SIOP_CTETS2_DDIR        0x80    /* Data Transfer Direction */
 435 #endif
 436 #define SIOP_CTEST2_SIGP        0x40    /* Signal process */
 437 #ifndef ARCH_720
 438 #define SIOP_CTEST2_SOFF        0x20    /* Synch Offset compare (1-> zero Init, max Tgt */
 439 #define SIOP_CTEST2_SFP         0x10    /* SCSI FIFO Parity */
 440 #else
 441 #define SIOP_CTEST2_RES5        0x20
 442 #define SIOP_CTEST2_RES4        0x10
 443 #endif
 444 #define SIOP_CTEST2_DFP         0x08    /* DMA FIFO Parity */
 445 #define SIOP_CTEST2_TEOP        0x04    /* True EOP (a-la 5380) */
 446 #define SIOP_CTEST2_DREQ        0x02    /* DREQ status */
 447 #define SIOP_CTEST2_DACK        0x01    /* DACK status */
 448
 449 /* Chip test register 3 (ctest3) read-only, top of SCSI FIFO */
 450
 451 #ifdef ARCH_720
 452 #define SIOP_CTEST3_V           0xf0    /* Chip revision level */
 453 #define SIOP_CTEST3_FLF         0x08    /* Flush DMA FIFO */
 454 #define SIOP_CTEST3_CLF         0x04    /* Clear DMA FIFO */
 455 #define SIOP_CTEST3_FM          0x02    /* Fetch pin mode */
 456 #define SIOP_CTEST3_SM          0x01    /* Snoop pins mode */
 457 #endif
 458
 459 /* Chip test register 4 (ctest4) */
 460
 461 #define SIOP_CTEST4_MUX         0x80    /* Host bus multiplex mode */
 462 #define SIOP_CTEST4_ZMOD        0x40    /* High-impedance outputs */
 463 #define SIOP_CTEST4_SZM         0x20    /* ditto, SCSI "outputs" */
 464 #ifndef ARCH_720
 465 #define SIOP_CTEST4_SLBE        0x10    /* SCSI loobpack enable */
 466 #define SIOP_CTEST4_SFWR        0x08    /* SCSI FIFO write enable (from sodl) */
 467 #else
 468 #define SIOP_CTEST4_SRTM        0x10    /* Shadow Register Test Mode */
 469 #define SIOP_CTEST4_EHPC        0x08    /* Enable Host Parity Check */
 470 #endif
 471 #define SIOP_CTEST4_FBL         0x07    /* DMA FIFO Byte Lane select (from ctest6)
 472                                            4->0, .. 7->3 */
 473
 474 /* Chip test register 5 (ctest5) */
 475
 476 #define SIOP_CTEST5_ADCK        0x80    /* Clock Address Incrementor */
 477 #define SIOP_CTEST5_BBCK        0x40    /* Clock Byte counter */
 478 #ifndef ARCH_720
 479 #define SIOP_CTEST5_ROFF        0x20    /* Reset SCSI offset */
 480 #else
 481 #define SIOP_CTEST5_RES         0x20
 482 #endif
 483 #define SIOP_CTEST5_MASR        0x10    /* Master set/reset pulses (of bits 3-0) */
 484 #define SIOP_CTEST5_DDIR        0x08    /* (re)set internal DMA direction */
 485 #ifndef ARCH_720
 486 #define SIOP_CTEST5_EOP         0x04    /* (re)set internal EOP */
 487 #define SIOP_CTEST5_DREQ        0x02    /* (re)set internal REQ */
 488 #define SIOP_CTEST5_DACK        0x01    /* (re)set internal ACK */
 489 #else
 490 #define SIOP_CTEST5_RAM         0x06    /* SCRIPTS RAM 1-0 */
 491 #define SIOP_CTEST5 RAMEN       0x01    /* RAM Base Address Enable */
 492 #endif
 493
 494 /* Chip test register 6 (ctest6)  DMA FIFO access */
 495
 496 /* Chip test register 7 (ctest7) */
 497
 498 #ifndef ARCH_720
 499 #define SIOP_CTEST7_CDIS        0x80    /* Cache burst disable */
 500 #define SIOP_CTEST7_SC1         0x40    /* Snoop control 1 */
 501 #define SIOP_CTEST7_SC0         0x20    /* Snoop contorl 0 */
 502 #define SIOP_CTEST7_STD         0x10    /* Selection timeout disable */
 503 #define SIOP_CTEST7_DFP         0x08    /* DMA FIFO parity bit */
 504 #define SIOP_CTEST7_EVP         0x04    /* Even parity (to host bus) */
 505 #define SIOP_CTEST7_TT1         0x02    /* Transfer type bit */
 506 #define SIOP_CTEST7_DIFF        0x01    /* Differential mode */
 507 #endif
 508
 509 /* DMA FIFO register (dfifo) */
 510
 511 #define SIOP_DFIFO_RES          0x80
 512 #define SIOP_DFIFO_BO           0x7f    /* FIFO byte offset counter */
 513
 514 /* Interrupt status register (istat) */
 515
 516 #define SIOP_ISTAT_ABRT         0x80    /* Abort operation */
 517 #define SIOP_ISTAT_RST          0x40    /* Software reset */
 518 #define SIOP_ISTAT_SIGP         0x20    /* Signal process */
 519 #ifndef ARCH_720
 520 #define SIOP_ISTAT_RES          0x10
 521 #else
 522 #define SIOP_ISTAT_SEM          0x10    /* Semaphore */
 523 #endif
 524 #define SIOP_ISTAT_CON          0x08    /* Connected */
 525 #ifndef ARCH_720
 526 #define SIOP_ISTAT_RES1         0x04
 527 #else
 528 #define SIOP_ISTAT_INTF         0x04    /* Interrupt on the Fly */
 529 #endif
 530 #define SIOP_ISTAT_SIP          0x02    /* SCSI Interrupt pending */
 531 #define SIOP_ISTAT_DIP          0x01    /* DMA Interrupt pending */
 532
 533 /* Chip test register 8 (ctest8) */
 534
 535 #define SIOP_CTEST8_V           0xf0    /* Chip revision level */
 536 #define SIOP_CTEST8_FLF         0x08    /* Flush DMA FIFO */
 537 #define SIOP_CTEST8_CLF         0x04    /* Clear DMA and SCSI FIFOs */
 538 #define SIOP_CTEST8_FM          0x02    /* Fetch pin mode */
 539 #define SIOP_CTEST8_SM          0x01    /* Snoop pins mode */
 540
 541 /* DMA Mode register (dmode) */
 542
 543 #define SIOP_DMODE_BL_MASK      0xc0    /* 0->1 1->2 2->4 3->8 */
 544 #define SIOP_DMODE_FC           0x30    /* Function code */
 545 #define SIOP_DMODE_PD           0x08    /* Program/data */
 546 #define SIOP_DMODE_FAM          0x04    /* Fixed address mode */
 547 #define SIOP_DMODE_U0           0x02    /* User programmable transfer type */
 548 #define SIOP_DMODE_MAN          0x01    /* Manual start mode */
 549
 550 /* DMA interrupt enable register (dien) */
 551
 552 #define SIOP_DIEN_RES           0xc0
 553 #ifdef ARCH_720
 554 #define SIOP_DIEN_HPED          0x40    /* Host Parity */
 555 #endif
 556 #define SIOP_DIEN_BF            0x20    /* On Bus Fault */
 557 #define SIOP_DIEN_ABRT          0x10    /* On Abort */
 558 #define SIOP_DIEN_SSI           0x08    /* On SCRIPTS sstep */
 559 #define SIOP_DIEN_SIR           0x04    /* On SCRIPTS intr instruction */
 560 #define SIOP_DIEN_WTD           0x02    /* On watchdog timeout */
 561 #define SIOP_DIEN_IID           0x01    /* On illegal instruction detected */
 562
 563 /* DMA control register (dcntl) */
 564
 565 #ifndef ARCH_720
 566 #define SIOP_DCNTL_CF_MASK      0xc0    /* Clock frequency dividers:
 567                                                 0 --> 37.51..50.00 MHz, div=2
 568                                                 1 --> 25.01..37.50 MHz, div=1.5
 569                                                 2 --> 16.67..25.00 MHz, div=1
 570                                                 3 --> 50.01..66.67 MHz, div=3
 571                                          */
 572 #else
 573 #define SIOP_DCNTL_STE          0x80    /* Size Throttle Enable */
 574 #define SIOP_DCNTL_BSM          0x40    /* Bus Mode */
 575 #endif
 576 #define SIOP_DCNTL_EA           0x20    /* Enable ack */
 577 #define SIOP_DCNTL_SSM          0x10    /* Single step mode */
 578 #ifndef ARCH_720
 579 #define SIOP_DCNTL_LLM          0x08    /* Enable SCSI Low-level mode */
 580 #else
 581 #define SIOP_DCNTL_BW16         0x8     /* Bus Width 16 */
 582 #endif
 583 #define SIOP_DCNTL_STD          0x04    /* Start DMA operation */
 584 #define SIOP_DCNTL_FA           0x02    /* Fast arbitration */
 585 #define SIOP_DCNTL_COM          0x01    /* 53C700 compatibility */