sys/arch/amiga/dev/wstsc.c

   1 /*      $NetBSD: wstsc.c,v 1.28.6.4 2005/11/10 13:51:36 skrll Exp $ */
   2
   3 /*
   4  * Copyright (c) 1982, 1990 The Regents of the University of California.
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  * 3. Neither the name of the University nor the names of its contributors
  16  *    may be used to endorse or promote products derived from this software
  17  *    without specific prior written permission.
  18  *
  19  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
  20  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  22  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  23  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  24  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  25  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  26  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  27  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  28  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  29  * SUCH DAMAGE.
  30  *
  31  *      @(#)supradma.c
  32  */
  33
  34 /*
  35  * Copyright (c) 1994 Michael L. Hitch
  36  *
  37  * Redistribution and use in source and binary forms, with or without
  38  * modification, are permitted provided that the following conditions
  39  * are met:
  40  * 1. Redistributions of source code must retain the above copyright
  41  *    notice, this list of conditions and the following disclaimer.
  42  * 2. Redistributions in binary form must reproduce the above copyright
  43  *    notice, this list of conditions and the following disclaimer in the
  44  *    documentation and/or other materials provided with the distribution.
  45  *
  46  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  47  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  48  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  49  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  50  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  51  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  52  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  53  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  54  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  55  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  56  *
  57  *      @(#)supradma.c
  58  */
  59
  60 #include <sys/cdefs.h>
  61 __KERNEL_RCSID(0, "$NetBSD: wstsc.c,v 1.28.6.4 2005/11/10 13:51:36 skrll Exp $");
  62
  63 #include <sys/param.h>
  64 #include <sys/systm.h>
  65 #include <sys/kernel.h>
  66 #include <sys/device.h>
  67 #include <dev/scsipi/scsi_all.h>
  68 #include <dev/scsipi/scsipi_all.h>
  69 #include <dev/scsipi/scsiconf.h>
  70 #include <amiga/amiga/device.h>
  71 #include <amiga/amiga/isr.h>
  72 #include <amiga/dev/scireg.h>
  73 #include <amiga/dev/scivar.h>
  74 #include <amiga/dev/zbusvar.h>
  75
  76 void wstscattach(struct device *, struct device *, void *);
  77 int wstscmatch(struct device *, struct cfdata *, void *);
  78
  79 int wstsc_dma_xfer_in(struct sci_softc *dev, int len,
  80     register u_char *buf, int phase);
  81 int wstsc_dma_xfer_out(struct sci_softc *dev, int len,
  82     register u_char *buf, int phase);
  83 int wstsc_dma_xfer_in2(struct sci_softc *dev, int len,
  84     register u_short *buf, int phase);
  85 int wstsc_dma_xfer_out2(struct sci_softc *dev, int len,
  86     register u_short *buf, int phase);
  87 int wstsc_intr(void *);
  88
  89 #ifdef DEBUG
  90 extern int sci_debug;
  91 #define QPRINTF(a) if (sci_debug > 1) printf a
  92 #else
  93 #define QPRINTF(a)
  94 #endif
  95
  96 extern int sci_data_wait;
  97
  98 int supradma_pseudo = 0;        /* 0=none, 1=byte, 2=word */
  99
 100 CFATTACH_DECL(wstsc, sizeof(struct sci_softc),
 101     wstscmatch, wstscattach, NULL, NULL);
 102
 103 /*
 104  * if this a Supra WordSync board
 105  */
 106 int
 107 wstscmatch(struct device *pdp, struct cfdata *cfp, void *auxp)
 108 {
 109         struct zbus_args *zap;
 110
 111         zap = auxp;
 112
 113         /*
 114          * Check manufacturer and product id.
 115          */
 116         if (zap->manid == 1056 && (
 117             zap->prodid == 12 ||        /* WordSync */
 118             zap->prodid == 13))         /* ByteSync */
 119                 return(1);
 120         else
 121                 return(0);
 122 }
 123
 124 void
 125 wstscattach(struct device *pdp, struct device *dp, void *auxp)
 126 {
 127         volatile u_char *rp;
 128         struct sci_softc *sc = (struct sci_softc *)dp;
 129         struct zbus_args *zap;
 130         struct scsipi_adapter *adapt = &sc->sc_adapter;
 131         struct scsipi_channel *chan = &sc->sc_channel;
 132
 133         printf("\n");
 134
 135         zap = auxp;
 136
 137         rp = zap->va;
 138         /*
 139          * set up 5380 register pointers
 140          * (Needs check on which Supra board this is - for now,
 141          *  just do the WordSync)
 142          */
 143         sc->sci_data = rp + 0;
 144         sc->sci_odata = rp + 0;
 145         sc->sci_icmd = rp + 2;
 146         sc->sci_mode = rp + 4;
 147         sc->sci_tcmd = rp + 6;
 148         sc->sci_bus_csr = rp + 8;
 149         sc->sci_sel_enb = rp + 8;
 150         sc->sci_csr = rp + 10;
 151         sc->sci_dma_send = rp + 10;
 152         sc->sci_idata = rp + 12;
 153         sc->sci_trecv = rp + 12;
 154         sc->sci_iack = rp + 14;
 155         sc->sci_irecv = rp + 14;
 156
 157         if (supradma_pseudo == 2) {
 158                 sc->dma_xfer_in = (int(*)(struct sci_softc *, int, u_char *, int))wstsc_dma_xfer_in2;
 159                 sc->dma_xfer_out = (int(*)(struct sci_softc *, int, u_char *, int))wstsc_dma_xfer_out2;
 160         }
 161         else if (supradma_pseudo == 1) {
 162                 sc->dma_xfer_in = wstsc_dma_xfer_in;
 163                 sc->dma_xfer_out = wstsc_dma_xfer_out;
 164         }
 165
 166         sc->sc_isr.isr_intr = wstsc_intr;
 167         sc->sc_isr.isr_arg = sc;
 168         sc->sc_isr.isr_ipl = 2;
 169         add_isr(&sc->sc_isr);
 170
 171         scireset(sc);
 172
 173         /*
 174          * Fill in the scsipi_adapter.
 175          */
 176         memset(adapt, 0, sizeof(*adapt));
 177         adapt->adapt_dev = &sc->sc_dev;
 178         adapt->adapt_nchannels = 1;
 179         adapt->adapt_openings = 7;
 180         adapt->adapt_max_periph = 1;
 181         adapt->adapt_request = sci_scsipi_request;
 182         adapt->adapt_minphys = sci_minphys;
 183
 184         /*
 185          * Fill in the scsipi_channel.
 186          */
 187         memset(chan, 0, sizeof(*chan));
 188         chan->chan_adapter = adapt;
 189         chan->chan_bustype = &scsi_bustype;
 190         chan->chan_channel = 0;
 191         chan->chan_ntargets = 8;
 192         chan->chan_nluns = 8;
 193         chan->chan_id = 7;
 194
 195         /*
 196          * attach all scsi units on us
 197          */
 198         config_found(dp, chan, scsiprint);
 199 }
 200
 201 int
 202 wstsc_dma_xfer_in(struct sci_softc *dev, int len, register u_char *buf,
 203                   int phase)
 204 {
 205         int wait = sci_data_wait;
 206         volatile register u_char *sci_dma = dev->sci_idata;
 207         volatile register u_char *sci_csr = dev->sci_csr;
 208 #ifdef DEBUG
 209         u_char *obp = (u_char *) buf;
 210 #endif
 211
 212         QPRINTF(("supradma_in %d, csr=%02x\n", len, *dev->sci_bus_csr));
 213
 214         *dev->sci_tcmd = phase;
 215         *dev->sci_icmd = 0;
 216         *dev->sci_mode = SCI_MODE_DMA;
 217         *dev->sci_irecv = 0;
 218
 219         while (len >= 128) {
 220                 wait = sci_data_wait;
 221                 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) !=
 222                   (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) {
 223                         if (!(*sci_csr & SCI_CSR_PHASE_MATCH)
 224                           || !(*dev->sci_bus_csr & SCI_BUS_BSY)
 225                           || --wait < 0) {
 226 #ifdef DEBUG
 227                                 if (sci_debug | 1)
 228                                         printf("supradma2_in fail: l%d i%x w%d\n",
 229                                         len, *dev->sci_bus_csr, wait);
 230 #endif
 231                                 *dev->sci_mode = 0;
 232                                 return 0;
 233                         }
 234                 }
 235
 236 #define R1      (*buf++ = *sci_dma)
 237                 R1; R1; R1; R1; R1; R1; R1; R1;
 238                 R1; R1; R1; R1; R1; R1; R1; R1;
 239                 R1; R1; R1; R1; R1; R1; R1; R1;
 240                 R1; R1; R1; R1; R1; R1; R1; R1;
 241                 R1; R1; R1; R1; R1; R1; R1; R1;
 242                 R1; R1; R1; R1; R1; R1; R1; R1;
 243                 R1; R1; R1; R1; R1; R1; R1; R1;
 244                 R1; R1; R1; R1; R1; R1; R1; R1;
 245                 R1; R1; R1; R1; R1; R1; R1; R1;
 246                 R1; R1; R1; R1; R1; R1; R1; R1;
 247                 R1; R1; R1; R1; R1; R1; R1; R1;
 248                 R1; R1; R1; R1; R1; R1; R1; R1;
 249                 R1; R1; R1; R1; R1; R1; R1; R1;
 250                 R1; R1; R1; R1; R1; R1; R1; R1;
 251                 R1; R1; R1; R1; R1; R1; R1; R1;
 252                 R1; R1; R1; R1; R1; R1; R1; R1;
 253                 len -= 128;
 254         }
 255
 256         while (len > 0) {
 257                 wait = sci_data_wait;
 258                 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) !=
 259                   (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) {
 260                         if (!(*sci_csr & SCI_CSR_PHASE_MATCH)
 261                           || !(*dev->sci_bus_csr & SCI_BUS_BSY)
 262                           || --wait < 0) {
 263 #ifdef DEBUG
 264                                 if (sci_debug | 1)
 265                                         printf("supradma1_in fail: l%d i%x w%d\n",
 266                                         len, *dev->sci_bus_csr, wait);
 267 #endif
 268                                 *dev->sci_mode = 0;
 269                                 return 0;
 270                         }
 271                 }
 272
 273                 *buf++ = *sci_dma;
 274                 len--;
 275         }
 276
 277         QPRINTF(("supradma_in {%d} %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
 278           len, obp[0], obp[1], obp[2], obp[3], obp[4], obp[5],
 279           obp[6], obp[7], obp[8], obp[9]));
 280
 281         *dev->sci_mode = 0;
 282         return 0;
 283 }
 284
 285 int
 286 wstsc_dma_xfer_out(struct sci_softc *dev, int len, register u_char *buf,
 287                    int phase)
 288 {
 289         int wait = sci_data_wait;
 290         volatile register u_char *sci_dma = dev->sci_data;
 291         volatile register u_char *sci_csr = dev->sci_csr;
 292
 293         QPRINTF(("supradma_out %d, csr=%02x\n", len, *dev->sci_bus_csr));
 294
 295         QPRINTF(("supradma_out {%d} %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
 296          len, buf[0], buf[1], buf[2], buf[3], buf[4], buf[5],
 297          buf[6], buf[7], buf[8], buf[9]));
 298
 299         *dev->sci_tcmd = phase;
 300         *dev->sci_mode = SCI_MODE_DMA;
 301         *dev->sci_icmd = SCI_ICMD_DATA;
 302         *dev->sci_dma_send = 0;
 303         while (len > 0) {
 304                 wait = sci_data_wait;
 305                 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) !=
 306                   (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) {
 307                         if (!(*sci_csr & SCI_CSR_PHASE_MATCH)
 308                           || !(*dev->sci_bus_csr & SCI_BUS_BSY)
 309                           || --wait < 0) {
 310 #ifdef DEBUG
 311                                 if (sci_debug)
 312                                         printf("supradma_out fail: l%d i%x w%d\n",
 313                                         len, *dev->sci_bus_csr, wait);
 314 #endif
 315                                 *dev->sci_mode = 0;
 316                                 return 0;
 317                         }
 318                 }
 319
 320                 *sci_dma = *buf++;
 321                 len--;
 322         }
 323
 324         wait = sci_data_wait;
 325         while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) ==
 326           SCI_CSR_PHASE_MATCH && --wait);
 327
 328
 329         *dev->sci_mode = 0;
 330         *dev->sci_icmd = 0;
 331         return 0;
 332 }
 333
 334
 335 int
 336 wstsc_dma_xfer_in2(struct sci_softc *dev, int len, register u_short *buf,
 337                    int phase)
 338 {
 339         volatile register u_short *sci_dma =
 340             (volatile u_short *)(dev->sci_idata + 0x10);
 341         volatile register u_char *sci_csr = dev->sci_csr + 0x10;
 342 #ifdef DEBUG
 343         u_char *obp = (u_char *) buf;
 344 #endif
 345 #if 0
 346         int wait = sci_data_wait;
 347 #endif
 348
 349         QPRINTF(("supradma_in2 %d, csr=%02x\n", len, *dev->sci_bus_csr));
 350
 351         *dev->sci_tcmd = phase;
 352         *dev->sci_mode = SCI_MODE_DMA;
 353         *dev->sci_icmd = 0;
 354         *(dev->sci_irecv + 16) = 0;
 355         while (len >= 128) {
 356 #if 0
 357                 wait = sci_data_wait;
 358                 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) !=
 359                   (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) {
 360                         if (!(*sci_csr & SCI_CSR_PHASE_MATCH)
 361                           || !(*dev->sci_bus_csr & SCI_BUS_BSY)
 362                           || --wait < 0) {
 363 #ifdef DEBUG
 364                                 if (sci_debug | 1)
 365                                         printf("supradma2_in2 fail: l%d i%x w%d\n",
 366                                         len, *dev->sci_bus_csr, wait);
 367 #endif
 368                                 *dev->sci_mode &= ~SCI_MODE_DMA;
 369                                 return 0;
 370                         }
 371                 }
 372 #else
 373                 while (!(*sci_csr & SCI_CSR_DREQ))
 374                         ;
 375 #endif
 376
 377 #define R2      (*buf++ = *sci_dma)
 378                 R2; R2; R2; R2; R2; R2; R2; R2;
 379                 R2; R2; R2; R2; R2; R2; R2; R2;
 380                 R2; R2; R2; R2; R2; R2; R2; R2;
 381                 R2; R2; R2; R2; R2; R2; R2; R2;
 382                 R2; R2; R2; R2; R2; R2; R2; R2;
 383                 R2; R2; R2; R2; R2; R2; R2; R2;
 384                 R2; R2; R2; R2; R2; R2; R2; R2;
 385                 R2; R2; R2; R2; R2; R2; R2; R2;
 386                 len -= 128;
 387         }
 388         while (len > 0) {
 389 #if 0
 390                 wait = sci_data_wait;
 391                 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) !=
 392                   (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) {
 393                         if (!(*sci_csr & SCI_CSR_PHASE_MATCH)
 394                           || !(*dev->sci_bus_csr & SCI_BUS_BSY)
 395                           || --wait < 0) {
 396 #ifdef DEBUG
 397                                 if (sci_debug | 1)
 398                                         printf("supradma1_in2 fail: l%d i%x w%d\n",
 399                                         len, *dev->sci_bus_csr, wait);
 400 #endif
 401                                 *dev->sci_mode &= ~SCI_MODE_DMA;
 402                                 return 0;
 403                         }
 404                 }
 405 #else
 406                 while (!(*sci_csr * SCI_CSR_DREQ))
 407                         ;
 408 #endif
 409
 410                 *buf++ = *sci_dma;
 411                 len -= 2;
 412         }
 413
 414         QPRINTF(("supradma_in2 {%d} %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
 415           len, obp[0], obp[1], obp[2], obp[3], obp[4], obp[5],
 416           obp[6], obp[7], obp[8], obp[9]));
 417
 418         *dev->sci_irecv = 0;
 419         *dev->sci_mode = 0;
 420         return 0;
 421 }
 422
 423 int
 424 wstsc_dma_xfer_out2(struct sci_softc *dev, int len, register u_short *buf,
 425                     int phase)
 426 {
 427         volatile register u_short *sci_dma =
 428             (volatile ushort *)(dev->sci_data + 0x10);
 429         volatile register u_char *sci_bus_csr = dev->sci_bus_csr;
 430 #ifdef DEBUG
 431         u_char *obp = (u_char *) buf;
 432 #endif
 433 #if 0
 434         int wait = sci_data_wait;
 435 #endif
 436
 437         QPRINTF(("supradma_out2 %d, csr=%02x\n", len, *dev->sci_bus_csr));
 438
 439         QPRINTF(("supradma_out2 {%d} %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
 440          len, obp[0], obp[1], obp[2], obp[3], obp[4], obp[5],
 441          obp[6], obp[7], obp[8], obp[9]));
 442
 443         *dev->sci_tcmd = phase;
 444         *dev->sci_mode = SCI_MODE_DMA;
 445         *dev->sci_icmd = SCI_ICMD_DATA;
 446         *dev->sci_dma_send = 0;
 447         while (len > 64) {
 448 #if 0
 449                 wait = sci_data_wait;
 450                 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) !=
 451                   (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) {
 452                         if (!(*sci_csr & SCI_CSR_PHASE_MATCH)
 453                           || !(*dev->sci_bus_csr & SCI_BUS_BSY)
 454                           || --wait < 0) {
 455 #ifdef DEBUG
 456                                 if (sci_debug)
 457                                         printf("supradma_out2 fail: l%d i%x w%d\n",
 458                                         len, csr, wait);
 459 #endif
 460                                 *dev->sci_mode = 0;
 461                                 return 0;
 462                         }
 463                 }
 464 #else
 465                 *dev->sci_mode = 0;
 466                 *dev->sci_icmd &= ~SCI_ICMD_ACK;
 467                 while (!(*sci_bus_csr & SCI_BUS_REQ))
 468                         ;
 469                 *dev->sci_mode = SCI_MODE_DMA;
 470                 *dev->sci_dma_send = 0;
 471 #endif
 472
 473 #define W2      (*sci_dma = *buf++)
 474                 W2; W2; W2; W2; W2; W2; W2; W2;
 475                 W2; W2; W2; W2; W2; W2; W2; W2;
 476                 if (*(sci_bus_csr + 0x10) & SCI_BUS_REQ)
 477                         ;
 478                 len -= 64;
 479         }
 480
 481         while (len > 0) {
 482 #if 0
 483                 wait = sci_data_wait;
 484                 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) !=
 485                   (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) {
 486                         if (!(*sci_csr & SCI_CSR_PHASE_MATCH)
 487                           || !(*dev->sci_bus_csr & SCI_BUS_BSY)
 488                           || --wait < 0) {
 489 #ifdef DEBUG
 490                                 if (sci_debug)
 491                                         printf("supradma_out2 fail: l%d i%x w%d\n",
 492                                         len, csr, wait);
 493 #endif
 494                                 *dev->sci_mode = 0;
 495                                 return 0;
 496                         }
 497                 }
 498 #else
 499                 *dev->sci_mode = 0;
 500                 *dev->sci_icmd &= ~SCI_ICMD_ACK;
 501                 while (!(*sci_bus_csr & SCI_BUS_REQ))
 502                         ;
 503                 *dev->sci_mode = SCI_MODE_DMA;
 504                 *dev->sci_dma_send = 0;
 505 #endif
 506
 507                 *sci_dma = *buf++;
 508                 if (*(sci_bus_csr + 0x10) & SCI_BUS_REQ)
 509                         ;
 510                 len -= 2;
 511         }
 512
 513 #if 0
 514         wait = sci_data_wait;
 515         while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) ==
 516           SCI_CSR_PHASE_MATCH && --wait);
 517 #endif
 518
 519
 520         *dev->sci_irecv = 0;
 521         *dev->sci_icmd &= ~SCI_ICMD_ACK;
 522         *dev->sci_mode = 0;
 523         *dev->sci_icmd = 0;
 524         return 0;
 525 }
 526
 527 int
 528 wstsc_intr(void *arg)
 529 {
 530         struct sci_softc *dev = arg;
 531         u_char stat;
 532
 533         if ((*(dev->sci_csr + 0x10) & SCI_CSR_INT) == 0)
 534                 return (0);
 535         stat = *(dev->sci_iack + 0x10);
 536         return (1);
 537 }