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Expand PMF_FN_* macros.
[netbsd-mini2440.git] / sys / arch / arm / include / arm32 / frame.h
blobfbb0effcb5065a465e65ddf5cccdb24c2a3af0e0
1 /* $NetBSD: frame.h,v 1.22 2009/01/17 22:56:34 bjh21 Exp $ */
2
3 /*
4 * Copyright (c) 1994-1997 Mark Brinicombe.
5 * Copyright (c) 1994 Brini.
6 * All rights reserved.
7 *
8 * This code is derived from software written for Brini by Mark Brinicombe
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. All advertising materials mentioning features or use of this software
19 * must display the following acknowledgement:
20 * This product includes software developed by Brini.
21 * 4. The name of the company nor the name of the author may be used to
22 * endorse or promote products derived from this software without specific
23 * prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
26 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
27 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
28 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
29 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
30 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
35 * SUCH DAMAGE.
36 *
37 * RiscBSD kernel project
38 *
39 * frame.h
40 *
41 * Stack frames structures
42 *
43 * Created : 30/09/94
44 */
45
46 #ifndef _ARM32_FRAME_H_
47 #define _ARM32_FRAME_H_
48
49 #include <arm/frame.h> /* Common ARM stack frames */
50
51 #ifndef _LOCORE
52
53 /*
54 * System stack frames.
55 */
56
57 typedef struct irqframe {
58 unsigned int if_spsr;
59 unsigned int if_r0;
60 unsigned int if_r1;
61 unsigned int if_r2;
62 unsigned int if_r3;
63 unsigned int if_r4;
64 unsigned int if_r5;
65 unsigned int if_r6;
66 unsigned int if_r7;
67 unsigned int if_r8;
68 unsigned int if_r9;
69 unsigned int if_r10;
70 unsigned int if_r11;
71 unsigned int if_r12;
72 unsigned int if_usr_sp;
73 unsigned int if_usr_lr;
74 unsigned int if_svc_sp;
75 unsigned int if_svc_lr;
76 unsigned int if_pc;
77 } irqframe_t;
78
79 struct clockframe {
80 struct irqframe cf_if;
81 };
82
83 /*
84 * Switch frame.
85 *
86 * Should be a multiple of 8 bytes for dumpsys.
87 */
88
89 struct switchframe {
90 u_int sf_r4;
91 u_int sf_r5;
92 u_int sf_r6;
93 u_int sf_r7;
94 u_int sf_sp;
95 u_int sf_pc;
96 };
97
98 /*
99 * Stack frame. Used during stack traces (db_trace.c)
100 */
101 struct frame {
102 u_int fr_fp;
103 u_int fr_sp;
104 u_int fr_lr;
105 u_int fr_pc;
106 };
107
108 #ifdef _KERNEL
109 void validate_trapframe(trapframe_t *, int);
110 #endif /* _KERNEL */
111
112 #else /* _LOCORE */
113
114 #include "opt_compat_netbsd.h"
115 #include "opt_execfmt.h"
116 #include "opt_multiprocessor.h"
117 #include "opt_cpuoptions.h"
118 #include "opt_arm_debug.h"
119
120 #include <machine/cpu.h>
121
122 /*
123 * This macro is used by DO_AST_AND_RESTORE_ALIGNMENT_FAULTS to process
124 * any pending softints.
125 */
126 #ifdef __HAVE_FAST_SOFTINTS
127 #define DO_PENDING_SOFTINTS \
128 ldr r0, [r4, #CI_INTR_DEPTH]/* Get current intr depth */ ;\
129 teq r0, #0 /* Test for 0. */ ;\
130 bne 10f /* skip softints if != 0 */ ;\
131 ldr r0, [r4, #CI_CPL] /* Get current priority level */;\
132 ldr r1, [r4, #CI_SOFTINTS] /* Get pending softint mask */ ;\
133 movs r0, r1, lsr r0 /* shift mask by cpl */ ;\
134 blne _C_LABEL(dosoftints) /* dosoftints(void) */ ;\
135 10:
136 #else
137 #define DO_PENDING_SOFTINTS /* nothing */
138 #endif
139
140 /*
141 * AST_ALIGNMENT_FAULT_LOCALS and ENABLE_ALIGNMENT_FAULTS
142 * These are used in order to support dynamic enabling/disabling of
143 * alignment faults when executing old a.out ARM binaries.
144 *
145 * Note that when ENABLE_ALIGNMENTS_FAULTS finishes r4 will contain
146 * pointer to the cpu's cpu_info. DO_AST_AND_RESTORE_ALIGNMENT_FAULTS
147 * relies on r4 being preserved.
148 */
149 #ifdef EXEC_AOUT
150 #define AST_ALIGNMENT_FAULT_LOCALS \
151 .Laflt_cpufuncs: ;\
152 .word _C_LABEL(cpufuncs)
153
154 /*
155 * This macro must be invoked following PUSHFRAMEINSVC or PUSHFRAME at
156 * the top of interrupt/exception handlers.
157 *
158 * When invoked, r0 *must* contain the value of SPSR on the current
159 * trap/interrupt frame. This is always the case if ENABLE_ALIGNMENT_FAULTS
160 * is invoked immediately after PUSHFRAMEINSVC or PUSHFRAME.
161 */
162 #define ENABLE_ALIGNMENT_FAULTS \
163 and r0, r0, #(PSR_MODE) /* Test for USR32 mode */ ;\
164 teq r0, #(PSR_USR32_MODE) ;\
165 GET_CURCPU(r4) /* r4 = cpuinfo */ ;\
166 bne 1f /* Not USR mode skip AFLT */ ;\
167 ldr r1, [r4, #CI_CURPCB] /* get curpcb from cpu_info */ ;\
168 ldr r1, [r1, #PCB_FLAGS] /* Fetch curpcb->pcb_flags */ ;\
169 tst r1, #PCB_NOALIGNFLT ;\
170 beq 1f /* AFLTs already enabled */ ;\
171 ldr r2, .Laflt_cpufuncs ;\
172 ldr r1, [r4, #CI_CTRL] /* Fetch control register */ ;\
173 mov r0, #-1 ;\
174 mov lr, pc ;\
175 ldr pc, [r2, #CF_CONTROL] /* Enable alignment faults */ ;\
176 1:
177
178 /*
179 * This macro must be invoked just before PULLFRAMEFROMSVCANDEXIT or
180 * PULLFRAME at the end of interrupt/exception handlers. We know that
181 * r4 points to cpu_info since that is what ENABLE_ALIGNMENT_FAULTS did
182 * for use.
183 */
184 #define DO_AST_AND_RESTORE_ALIGNMENT_FAULTS \
185 DO_PENDING_SOFTINTS ;\
186 ldr r0, [sp] /* Get the SPSR from stack */ ;\
187 mrs r5, cpsr /* save CPSR */ ;\
188 orr r1, r5, #(IF32_bits) ;\
189 msr cpsr_c, r1 /* Disable interrupts */ ;\
190 and r0, r0, #(PSR_MODE) /* Returning to USR mode? */ ;\
191 teq r0, #(PSR_USR32_MODE) ;\
192 bne 3f /* Nope, get out now */ ;\
193 1: ldr r1, [r4, #CI_ASTPENDING] /* Pending AST? */ ;\
194 teq r1, #0x00000000 ;\
195 bne 2f /* Yup. Go deal with it */ ;\
196 ldr r1, [r4, #CI_CURPCB] /* Get current PCB */ ;\
197 ldr r0, [r1, #PCB_FLAGS] /* Fetch curpcb->pcb_flags */ ;\
198 tst r0, #PCB_NOALIGNFLT ;\
199 beq 3f /* Keep AFLTs enabled */ ;\
200 ldr r1, [r4, #CI_CTRL] /* Fetch control register */ ;\
201 ldr r2, .Laflt_cpufuncs ;\
202 mov r0, #-1 ;\
203 bic r1, r1, #CPU_CONTROL_AFLT_ENABLE /* Disable AFLTs */ ;\
204 adr lr, 3f ;\
205 ldr pc, [r2, #CF_CONTROL] /* Set new CTRL reg value */ ;\
206 /* NOTREACHED */ \
207 2: mov r1, #0x00000000 ;\
208 str r1, [r4, #CI_ASTPENDING] /* Clear astpending */ ;\
209 bic r5, r5, #(IF32_bits) ;\
210 msr cpsr_c, r5 /* Restore interrupts */ ;\
211 mov r0, sp ;\
212 bl _C_LABEL(ast) /* ast(frame) */ ;\
213 orr r0, r5, #(IF32_bits) /* Disable IRQs */ ;\
214 msr cpsr_c, r0 ;\
215 b 1b /* Back around again */ ;\
216 3:
217
218 #else /* !EXEC_AOUT */
219
220 #define AST_ALIGNMENT_FAULT_LOCALS
221
222 #define ENABLE_ALIGNMENT_FAULTS GET_CURCPU(r4)
223
224 #define DO_AST_AND_RESTORE_ALIGNMENT_FAULTS \
225 DO_PENDING_SOFTINTS ;\
226 ldr r0, [sp] /* Get the SPSR from stack */ ;\
227 mrs r5, cpsr /* save CPSR */ ;\
228 orr r1, r5, #(IF32_bits) ;\
229 msr cpsr_c, r1 /* Disable interrupts */ ;\
230 and r0, r0, #(PSR_MODE) /* Returning to USR mode? */ ;\
231 teq r0, #(PSR_USR32_MODE) ;\
232 bne 2f /* Nope, get out now */ ;\
233 1: ldr r1, [r4, #CI_ASTPENDING] /* Pending AST? */ ;\
234 teq r1, #0x00000000 ;\
235 beq 2f /* Nope. Just bail */ ;\
236 mov r1, #0x00000000 ;\
237 str r1, [r4, #CI_ASTPENDING] /* Clear astpending */ ;\
238 bic r5, r5, #(IF32_bits) ;\
239 msr cpsr_c, r5 /* Restore interrupts */ ;\
240 mov r0, sp ;\
241 bl _C_LABEL(ast) /* ast(frame) */ ;\
242 orr r0, r5, #(IF32_bits) /* Disable IRQs */ ;\
243 msr cpsr_c, r0 ;\
244 b 1b ;\
245 2:
246 #endif /* EXEC_AOUT */
247
248 #ifdef ARM_LOCK_CAS_DEBUG
249 #define LOCK_CAS_DEBUG_LOCALS \
250 .L_lock_cas_restart: ;\
251 .word _C_LABEL(_lock_cas_restart)
252
253 #if defined(__ARMEB__)
254 #define LOCK_CAS_DEBUG_COUNT_RESTART \
255 ble 99f ;\
256 ldr r0, .L_lock_cas_restart ;\
257 ldmia r0, {r1-r2} /* load ev_count */ ;\
258 adds r2, r2, #1 /* 64-bit incr (lo) */ ;\
259 adc r1, r1, #0 /* 64-bit incr (hi) */ ;\
260 stmia r0, {r1-r2} /* store ev_count */
261 #else /* __ARMEB__ */
262 #define LOCK_CAS_DEBUG_COUNT_RESTART \
263 ble 99f ;\
264 ldr r0, .L_lock_cas_restart ;\
265 ldmia r0, {r1-r2} /* load ev_count */ ;\
266 adds r1, r1, #1 /* 64-bit incr (lo) */ ;\
267 adc r2, r2, #0 /* 64-bit incr (hi) */ ;\
268 stmia r0, {r1-r2} /* store ev_count */
269 #endif /* __ARMEB__ */
270 #else /* ARM_LOCK_CAS_DEBUG */
271 #define LOCK_CAS_DEBUG_LOCALS /* nothing */
272 #define LOCK_CAS_DEBUG_COUNT_RESTART /* nothing */
273 #endif /* ARM_LOCK_CAS_DEBUG */
274
275 #define LOCK_CAS_CHECK_LOCALS \
276 .L_lock_cas: ;\
277 .word _C_LABEL(_lock_cas) ;\
278 .L_lock_cas_end: ;\
279 .word _C_LABEL(_lock_cas_end) ;\
280 LOCK_CAS_DEBUG_LOCALS
281
282 #define LOCK_CAS_CHECK \
283 ldr r0, [sp] /* get saved PSR */ ;\
284 and r0, r0, #(PSR_MODE) /* check for SVC32 mode */ ;\
285 teq r0, #(PSR_SVC32_MODE) ;\
286 bne 99f /* nope, get out now */ ;\
287 ldr r0, [sp, #(IF_PC)] ;\
288 ldr r1, .L_lock_cas_end ;\
289 cmp r0, r1 ;\
290 bge 99f ;\
291 ldr r1, .L_lock_cas ;\
292 cmp r0, r1 ;\
293 strgt r1, [sp, #(IF_PC)] ;\
294 LOCK_CAS_DEBUG_COUNT_RESTART ;\
295 99:
296
297 /*
298 * ASM macros for pushing and pulling trapframes from the stack
299 *
300 * These macros are used to handle the irqframe and trapframe structures
301 * defined above.
302 */
303
304 /*
305 * PUSHFRAME - macro to push a trap frame on the stack in the current mode
306 * Since the current mode is used, the SVC lr field is not defined.
307 *
308 * NOTE: r13 and r14 are stored separately as a work around for the
309 * SA110 rev 2 STM^ bug
310 */
311
312 #define PUSHFRAME \
313 str lr, [sp, #-4]!; /* Push the return address */ \
314 sub sp, sp, #(4*17); /* Adjust the stack pointer */ \
315 stmia sp, {r0-r12}; /* Push the user mode registers */ \
316 add r0, sp, #(4*13); /* Adjust the stack pointer */ \
317 stmia r0, {r13-r14}^; /* Push the user mode registers */ \
318 mov r0, r0; /* NOP for previous instruction */ \
319 mrs r0, spsr_all; /* Put the SPSR on the stack */ \
320 str r0, [sp, #-4]!
321
322 /*
323 * PULLFRAME - macro to pull a trap frame from the stack in the current mode
324 * Since the current mode is used, the SVC lr field is ignored.
325 */
326
327 #define PULLFRAME \
328 ldr r0, [sp], #0x0004; /* Get the SPSR from stack */ \
329 msr spsr_all, r0; \
330 ldmia sp, {r0-r14}^; /* Restore registers (usr mode) */ \
331 mov r0, r0; /* NOP for previous instruction */ \
332 add sp, sp, #(4*17); /* Adjust the stack pointer */ \
333 ldr lr, [sp], #0x0004 /* Pull the return address */
334
335 /*
336 * PUSHFRAMEINSVC - macro to push a trap frame on the stack in SVC32 mode
337 * This should only be used if the processor is not currently in SVC32
338 * mode. The processor mode is switched to SVC mode and the trap frame is
339 * stored. The SVC lr field is used to store the previous value of
340 * lr in SVC mode.
341 *
342 * NOTE: r13 and r14 are stored separately as a work around for the
343 * SA110 rev 2 STM^ bug
344 */
345
346 #define PUSHFRAMEINSVC \
347 stmdb sp, {r0-r3}; /* Save 4 registers */ \
348 mov r0, lr; /* Save xxx32 r14 */ \
349 mov r1, sp; /* Save xxx32 sp */ \
350 mrs r3, spsr; /* Save xxx32 spsr */ \
351 mrs r2, cpsr; /* Get the CPSR */ \
352 bic r2, r2, #(PSR_MODE); /* Fix for SVC mode */ \
353 orr r2, r2, #(PSR_SVC32_MODE); \
354 msr cpsr_c, r2; /* Punch into SVC mode */ \
355 mov r2, sp; /* Save SVC sp */ \
356 str r0, [sp, #-4]!; /* Push return address */ \
357 str lr, [sp, #-4]!; /* Push SVC lr */ \
358 str r2, [sp, #-4]!; /* Push SVC sp */ \
359 msr spsr_all, r3; /* Restore correct spsr */ \
360 ldmdb r1, {r0-r3}; /* Restore 4 regs from xxx mode */ \
361 sub sp, sp, #(4*15); /* Adjust the stack pointer */ \
362 stmia sp, {r0-r12}; /* Push the user mode registers */ \
363 add r0, sp, #(4*13); /* Adjust the stack pointer */ \
364 stmia r0, {r13-r14}^; /* Push the user mode registers */ \
365 mov r0, r0; /* NOP for previous instruction */ \
366 mrs r0, spsr_all; /* Put the SPSR on the stack */ \
367 str r0, [sp, #-4]!
368
369 /*
370 * PULLFRAMEFROMSVCANDEXIT - macro to pull a trap frame from the stack
371 * in SVC32 mode and restore the saved processor mode and PC.
372 * This should be used when the SVC lr register needs to be restored on
373 * exit.
374 */
375
376 #define PULLFRAMEFROMSVCANDEXIT \
377 ldr r0, [sp], #0x0004; /* Get the SPSR from stack */ \
378 msr spsr_all, r0; /* restore SPSR */ \
379 ldmia sp, {r0-r14}^; /* Restore registers (usr mode) */ \
380 mov r0, r0; /* NOP for previous instruction */ \
381 add sp, sp, #(4*15); /* Adjust the stack pointer */ \
382 ldmia sp, {sp, lr, pc}^ /* Restore lr and exit */
383
384 #endif /* _LOCORE */
385
386 #endif /* _ARM32_FRAME_H_ */
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