sys/arch/arm/iomd/iomdreg.h

   1 /*      $NetBSD: iomdreg.h,v 1.2.20.3 2004/09/21 13:13:19 skrll Exp $   */
   2
   3 /*
   4  * Copyright (c) 1994-1997 Mark Brinicombe.
   5  * Copyright (c) 1994 Brini.
   6  * All rights reserved.
   7  *
   8  * This code is derived from software written for Brini by Mark Brinicombe
   9  *
  10  * Redistribution and use in source and binary forms, with or without
  11  * modification, are permitted provided that the following conditions
  12  * are met:
  13  * 1. Redistributions of source code must retain the above copyright
  14  *    notice, this list of conditions and the following disclaimer.
  15  * 2. Redistributions in binary form must reproduce the above copyright
  16  *    notice, this list of conditions and the following disclaimer in the
  17  *    documentation and/or other materials provided with the distribution.
  18  * 3. All advertising materials mentioning features or use of this software
  19  *    must display the following acknowledgement:
  20  *      This product includes software developed by Mark Brinicombe.
  21  * 4. The name of the company nor the name of the author may be used to
  22  *    endorse or promote products derived from this software without specific
  23  *    prior written permission.
  24  *
  25  * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
  26  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  27  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  28  * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
  29  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  30  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  31  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  32  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  33  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  34  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  35  * SUCH DAMAGE.
  36  *
  37  * RiscBSD kernel project
  38  *
  39  * iomd.h
  40  *
  41  * IOMD registers
  42  *
  43  * Created      : 18/09/94
  44  *
  45  * Based on kate/display/iomd.h
  46  */
  47
  48 #define IOMD_HW_BASE    0x03200000
  49
  50 #define IOMD_BASE       0xf6000000
  51
  52 #define IOMD_IOCR       0x00000000
  53 #define IOMD_KBDDAT     0x00000001
  54 #define IOMD_KBDCR      0x00000002
  55 #define IOMD_IOLINES    0x00000003      /* ARM7500FE */
  56
  57 #define IOMD_IRQSTA     0x00000004
  58 #define IOMD_IRQRQA     0x00000005
  59 #define IOMD_IRQMSKA    0x00000006
  60 #define IOMD_SUSMODE    0x00000007      /* ARM7500 */
  61
  62 #define IOMD_IRQSTB     0x00000008
  63 #define IOMD_IRQRQB     0x00000009
  64 #define IOMD_IRQMSKB    0x0000000a
  65 #define IOMD_STOPMODE   0x0000000b      /* ARM7500 */
  66
  67 #define IOMD_FIQST      0x0000000c
  68 #define IOMD_FIQRQ      0x0000000d
  69 #define IOMD_FIQMSK     0x0000000e
  70 #define IOMD_CLKCTL     0x0000000f      /* ARM7500 */
  71
  72 #define IOMD_T0LOW      0x00000010
  73 #define IOMD_T0HIGH     0x00000011
  74 #define IOMD_T0GO       0x00000012
  75 #define IOMD_T0LATCH    0x00000013
  76
  77 #define IOMD_T1LOW      0x00000014
  78 #define IOMD_T1HIGH     0x00000015
  79 #define IOMD_T1GO       0x00000016
  80 #define IOMD_T1LATCH    0x00000017
  81
  82 /*
  83  * For ARM7500, it's not really a IOMD device.
  84  */
  85
  86 #define IOMD_IRQSTC     0x00000018      /* ARM7500 */
  87 #define IOMD_IRQRQC     0x00000019      /* ARM7500 */
  88 #define IOMD_IRQMSKC    0x0000001a      /* ARM7500 */
  89 #define IOMD_VIDMUX     0x0000001b      /* ARM7500 */
  90
  91 #define IOMD_IRQSTD     0x0000001c      /* ARM7500 */
  92 #define IOMD_IRQRQD     0x0000001d      /* ARM7500 */
  93 #define IOMD_IRQMSKD    0x0000001e      /* ARM7500 */
  94
  95 #define IOMD_ROMCR0     0x00000020
  96 #define IOMD_ROMCR1     0x00000021
  97 #define IOMD_DRAMCR     0x00000022      /* !ARM7500 */
  98 #define IOMD_VREFCR     0x00000023      /* !ARM7500 */
  99 #define IOMD_REFCR      0x00000023      /* ARM7500 */
 100
 101 #define IOMD_FSIZE      0x00000024
 102 #define IOMD_ID0        0x00000025
 103 #define IOMD_ID1        0x00000026
 104 #define IOMD_VERSION    0x00000027
 105
 106 #define IOMD_MOUSEX     0x00000028
 107 #define IOMD_MOUSEY     0x00000029
 108 #define IOMD_MSDATA     0x0000002a      /* ARM7500 */
 109 #define IOMD_MSCR       0x0000002b      /* ARM7500 */
 110
 111 #define IOMD_DMATCR     0x00000030
 112 #define IOMD_IOTCR      0x00000031
 113 #define IOMD_ECTCR      0x00000032
 114 #define IOMD_DMAEXT     0x00000033      /* !ARM7500 */
 115 #define IOMD_ASTCR      0x00000033      /* ARM7500 */
 116
 117 #define IOMD_DRAMWID    0x00000034      /* ARM7500 */
 118 #define IOMD_SELFREF    0x00000035      /* ARM7500 */
 119
 120 #define IOMD_ATODICR    0x00000038      /* ARM7500 */
 121 #define IOMD_ATODSR     0x00000039      /* ARM7500 */
 122 #define IOMD_ATODCR     0x0000003a      /* ARM7500 */
 123 #define IOMD_ATODCNT1   0x0000003b      /* ARM7500 */
 124 #define IOMD_ATODCNT2   0x0000003c      /* ARM7500 */
 125 #define IOMD_ATODCNT3   0x0000003d      /* ARM7500 */
 126 #define IOMD_ATODCNT4   0x0000003e      /* ARM7500 */
 127
 128 #define IOMD_DMA_SIZE           24
 129 #define IOMD_DMA_SPACING        32
 130 /* Each DMA channel has the same set of registers. */
 131 #define IOMD_DMAEND_STOP        0x80000000
 132 #define IOMD_DMAEND_LAST        0x40000000
 133 #define IOMD_DMAEND_OFFSET      0x00000fff
 134 #define IOMD_DMACR_CLEAR        0x80
 135 #define IOMD_DMACR_DIR          0x40
 136 #define IOMD_DMACR_ENABLE       0x20
 137 #define IOMD_DMACR_BYTE         0x01
 138 #define IOMD_DMACR_HALFWORD     0x02
 139 #define IOMD_DMACR_WORD         0x04
 140 #define IOMD_DMACR_QUADWORD     0x10
 141 #define IOMD_DMAST_OVERRUN      0x04
 142 #define IOMD_DMAST_INT          0x02
 143 #define IOMD_DMAST_BANKB        0x01
 144 #define IOMD_DMAST_BANKA        0x00
 145
 146 #define IOMD_IO0CURA    0x00000040
 147 #define IOMD_IO0ENDA    0x00000041
 148 #define IOMD_IO0CURB    0x00000042
 149 #define IOMD_IO0ENDB    0x00000043
 150 #define IOMD_IO0CR      0x00000044
 151 #define IOMD_IO0ST      0x00000045
 152 #define IOMD_IO1CURA    0x00000048
 153 #define IOMD_IO1ENDA    0x00000049
 154 #define IOMD_IO1CURB    0x0000004a
 155 #define IOMD_IO1ENDB    0x0000004b
 156 #define IOMD_IO1CR      0x0000004c
 157 #define IOMD_IO1ST      0x0000004d
 158 #define IOMD_IO2CURA    0x00000050
 159 #define IOMD_IO2ENDA    0x00000051
 160 #define IOMD_IO2CURB    0x00000052
 161 #define IOMD_IO2ENDB    0x00000053
 162 #define IOMD_IO2CR      0x00000054
 163 #define IOMD_IO2ST      0x00000055
 164 #define IOMD_IO3CURA    0x00000058
 165 #define IOMD_IO3ENDA    0x00000059
 166 #define IOMD_IO3CURB    0x0000005a
 167 #define IOMD_IO3ENDB    0x0000005b
 168 #define IOMD_IO3CR      0x0000005c
 169 #define IOMD_IO3ST      0x0000005d
 170
 171 #define IOMD_SD0CURA    0x00000060
 172 #define IOMD_SD0ENDA    0x00000061
 173 #define IOMD_SD0CURB    0x00000062
 174 #define IOMD_SD0ENDB    0x00000063
 175 #define IOMD_SD0CR      0x00000064
 176 #define IOMD_SD0ST      0x00000065
 177
 178 #define IOMD_SD1CURA    0x00000068
 179 #define IOMD_SD1ENDA    0x00000069
 180 #define IOMD_SD1CURB    0x0000006a
 181 #define IOMD_SD1ENDB    0x0000006b
 182 #define IOMD_SD1CR      0x0000006c
 183 #define IOMD_SD1ST      0x0000006d
 184
 185 #define IOMD_CURSCUR    0x00000070
 186 #define IOMD_CURSINIT   0x00000071
 187 #define IOMD_VIDCURB    0x00000072      /* ARM7500 */
 188
 189 #define IOMD_VIDCUR     0x00000074
 190 #define IOMD_VIDEND     0x00000075
 191 #define IOMD_VIDSTART   0x00000076
 192 #define IOMD_VIDINIT    0x00000077
 193 #define IOMD_VIDCR      0x00000078
 194
 195 #define IOMD_VIDINITB   0x0000007a      /* ARM7500 */
 196
 197 #define IOMD_DMAST      0x0000007c
 198 #define IOMD_DMARQ      0x0000007d
 199 #define IOMD_DMAMSK     0x0000007e
 200
 201 #define IOMD_SIZE       0x100   /* XXX - should be words ? */
 202
 203 /*
 204  * Ok these mouse buttons are not strickly part of the iomd but
 205  * this register is required if the IOMD supports a quadrature mouse
 206  */
 207
 208 #define IO_HW_MOUSE_BUTTONS     0x03210000
 209 #define IO_MOUSE_BUTTONS        0xf6010000
 210
 211 #define MOUSE_BUTTON_RIGHT  0x10
 212 #define MOUSE_BUTTON_MIDDLE 0x20
 213 #define MOUSE_BUTTON_LEFT   0x40
 214
 215 #define FREQCON (iomd_base + 0x40000)
 216
 217 #define RPC600_IOMD_ID          0xd4e7
 218 #define ARM7500_IOC_ID          0x5b98
 219 #define ARM7500FE_IOC_ID        0xaa7c
 220
 221 #define IOMD_ADDRESS(reg)       (iomd_base + (reg << 2))
 222 #define IOMD_WRITE_BYTE(reg, val)       \
 223         (*((volatile unsigned char *)(IOMD_ADDRESS(reg))) = (val))
 224 #define IOMD_WRITE_WORD(reg, val)       \
 225         (*((volatile unsigned int *)(IOMD_ADDRESS(reg))) = (val))
 226 #define IOMD_READ_BYTE(reg)             \
 227         (*((volatile unsigned char *)(IOMD_ADDRESS(reg))))
 228 #define IOMD_READ_WORD(reg)             \
 229         (*((volatile unsigned int *)(IOMD_ADDRESS(reg))))
 230
 231 #define IOMD_ID (IOMD_READ_BYTE(IOMD_ID0) | (IOMD_READ_BYTE(IOMD_ID1) << 8))
 232
 233 /* End of iomdreg.h */