sys/arch/arm/sa11x0/sa1111_reg.h

   1 /*      $NetBSD: sa1111_reg.h,v 1.3 2002/12/18 04:09:31 bsh Exp $       */
   2
   3 /*-
   4  * Copyright (c) 2001 The NetBSD Foundation, Inc.
   5  * All rights reserved.
   6  *
   7  * This code is derived from software contributed to The NetBSD Foundation
   8  * by IWAMOTO Toshihiro.
   9  *
  10  * Redistribution and use in source and binary forms, with or without
  11  * modification, are permitted provided that the following conditions
  12  * are met:
  13  * 1. Redistributions of source code must retain the above copyright
  14  *    notice, this list of conditions and the following disclaimer.
  15  * 2. Redistributions in binary form must reproduce the above copyright
  16  *    notice, this list of conditions and the following disclaimer in the
  17  *    documentation and/or other materials provided with the distribution.
  18  *
  19  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
  20  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  21  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  22  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  23  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  29  * POSSIBILITY OF SUCH DAMAGE.
  30  */
  31
  32 #ifndef _ARM_SA11X0_SA1111_REG_H
  33 #define _ARM_SA11X0_SA1111_REG_H
  34
  35
  36 /* Interrupt Controller */
  37
  38 /* number of interrupt bits */
  39 #define SACCIC_LEN      55
  40
  41 /* System Bus Interface */
  42 #define SACCSBI_SKCR            0x0000
  43 #define  SKCR_PLLBYPASS         (1<<0)
  44 #define  SKCR_RCLKEN            (1<<1)
  45 #define  SKCR_SLEEP             (1<<2)
  46 #define  SKCR_DOZE              (1<<3)
  47 #define  SKCR_VCOOFF            (1<<4)
  48 #define  SKCR_RDYEN             (1<<7)
  49 #define  SKCR_SELAC             (1<<8)  /* AC Link or I2S */
  50 #define  SKCR_NOEEN             (1<<12) /* Enable nOE */
  51 #define SACCSBI_SMCR            0x0004
  52 #define SACCSBI_SKID            0x0008
  53
  54 /* System Controller */
  55 #define SACCSC_SKPCR            0x0200
  56
  57 /* USB Host Controller */
  58 #define SACCUSB_REVISION        0x0400
  59 #define SACCUSB_CONTROL         0x0404
  60 #define SACCUSB_STATUS          0x0408
  61 #define SACCUSB_RESET           0x051C
  62
  63 /* Interrupt Controller */
  64 #define SACCIC_INTTEST0         0x1600
  65 #define SACCIC_INTTEST1         0x1604
  66 #define SACCIC_INTEN0           0x1608
  67 #define SACCIC_INTEN1           0x160C
  68 #define SACCIC_INTPOL0          0x1610
  69 #define SACCIC_INTPOL1          0x1614
  70 #define SACCIC_INTTSTSEL        0x1618
  71 #define SACCIC_INTSTATCLR0      0x161C
  72 #define SACCIC_INTSTATCLR1      0x1620
  73 #define SACCIC_INTSET0          0x1624
  74 #define SACCIC_INTSET1          0x1628
  75 #define SACCIC_WAKE_EN0         0x162C
  76 #define SACCIC_WAKE_EN1         0x1630
  77 #define SACCIC_WAKE_POL0        0x1634
  78 #define SACCIC_WAKE_POL1        0x1638
  79
  80 /* GPIO registers */
  81 #define SACCGPIOA_DDR           0x1000          /* data direction */
  82 #define SACCGPIOA_DVR           0x1004          /* data value */
  83 #define SACCGPIOA_SDR           0x1008          /* sleep direction */
  84 #define SACCGPIOA_SSR           0x100C          /* sleep state */
  85 #define SACCGPIOB_DDR           0x1010
  86 #define SACCGPIOB_DVR           0x1014
  87 #define SACCGPIOB_SDR           0x1018
  88 #define SACCGPIOB_SSR           0x101C
  89 #define SACCGPIOC_DDR           0x1020
  90 #define SACCGPIOC_DVR           0x1024
  91 #define SACCGPIOC_SDR           0x1028
  92 #define SACCGPIOC_SSR           0x102C
  93
  94 #define SACC_KBD0               0x0a00
  95 #define SACC_KBD1               0x0c00
  96
  97 #define SACCKBD_CR              0x00
  98 #define  KBDCR_FKC              (1<<0) /* Force MSCLK/TPCLK low */
  99 #define  KBDCR_FKD              (1<<1) /* Force MSDATA/TPDATA low */
 100 #define  KBDCR_ENA              (1<<3) /* Enable */
 101 #define SACCKBD_STAT            0x04
 102 #define  KBDSTAT_KBC            (1<<0) /* KBCLK pin value */
 103 #define  KBDSTAT_KBD            (1<<1) /* KBDATA pin value */
 104 #define  KBDSTAT_RXP            (1<<2) /* Parity */
 105 #define  KBDSTAT_ENA            (1<<3) /* Enable */
 106 #define  KBDSTAT_RXB            (1<<4) /* Rx busy */
 107 #define  KBDSTAT_RXF            (1<<5) /* Rx full */
 108 #define  KBDSTAT_TXB            (1<<6) /* Tx busy */
 109 #define  KBDSTAT_TXE            (1<<7) /* Tx empty */
 110 #define  KBDSTAT_STP            (1<<8) /* Stop bit error */
 111 #define SACCKBD_DATA            0x08
 112 #define SACCKBD_CLKDIV          0x0c
 113 #define  KBDCLKDIV_DIV8         0
 114 #define  KBDCLKDIV_DIV4         1
 115 #define  KBDCLKDIV_DIV2         2
 116 #define SACCKBD_CLKPRECNT       0x10
 117 #define SACCKBD_KBDITR          0x14 /* Interrupt test */
 118
 119 #define SACCKBD_SIZE            0x18
 120
 121 #endif /* _ARM_SA11X0_SA1111_REG_H */