sys/arch/arm/sa11x0/sa11x0_mcpreg.h

   1 /*      $NetBSD: sa11x0_mcpreg.h,v 1.1 2001/07/30 10:17:21 rjs Exp $    */
   2
   3 /*-
   4  * Copyright (c) 2001 The NetBSD Foundation, Inc.  All rights reserved.
   5  *
   6  * This code is derived from software contributed to The NetBSD Foundation
   7  * by Ichiro FUKUHARA (ichiro@ichiro.org).
   8  *
   9  * Redistribution and use in source and binary forms, with or without
  10  * modification, are permitted provided that the following conditions
  11  * are met:
  12  * 1. Redistributions of source code must retain the above copyright
  13  *    notice, this list of conditions and the following disclaimer.
  14  * 2. Redistributions in binary form must reproduce the above copyright
  15  *    notice, this list of conditions and the following disclaimer in the
  16  *    documentation and/or other materials provided with the distribution.
  17  *
  18  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
  19  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  20  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  21  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  22  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  23  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  24  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  25  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  26  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  27  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  28  * POSSIBILITY OF SUCH DAMAGE.
  29  */
  30
  31 /* SA11[01]0 MCP(Multimedia communications Port) */
  32
  33 #define SAMCP_NPORTS    7
  34
  35 #define SAMCP_CR0       0x00    /* MCP control register 0 */
  36 /* MCP control register 1 locate PPC area */
  37
  38 #define SAMCP_DR0       0x08    /* MCP data register 0 */
  39 #define SAMCP_DR1       0x0C    /* MCP data register 1 */
  40 #define SAMCP_DR2       0x10    /* MCP data register 2 */
  41 #define SAMCP_SR        0x18    /* MCP status register */
  42
  43 /* MCP control register 0*/
  44 #define CR0_ASD
  45 #define CR0_TSD
  46 #define CR0_MCE         (1 << 16)       /* MCP enable */
  47 #define CR0_ECS         (1 << 17)       /* External clock used */
  48 #define CR0_ADM         (1 << 18)       /* A/D sampling mode */
  49 #define CR0_TTE         (1 << 19)       /* Telecom tx FIFO intr enable */
  50 #define CR0_TRE         (1 << 20)       /* Telecom rx FIFO intr enable */
  51 #define CR0_ATE         (1 << 21)       /* Audio tx FIFO intr enable */
  52 #define CR0_ARE         (1 << 22)       /* Audio rx FIFO intr enable */
  53 #define CR0_LBM         (1 << 23)       /* Output of serial shifter connect
  54                                            to Input of serial shifter internal */
  55 #define CR0_ECP(x)      ((x) << 24)     /* External clock prescaler */
  56
  57 /* MCP control register 0 */
  58 #define CR1_CFS         (1 << 20)
  59
  60 /* MCP status register */
  61 #define SR_ATS          (1 << 0)        /* Audio transmit FIFO req-flag */
  62 #define SR_ARS          (1 << 1)        /* Audio receive FIFO req */
  63 #define SR_TTS          (1 << 2)        /* Telecom transmit FIFO req-flag */
  64 #define SR_TRS          (1 << 3)        /* Telecom receive FIFO req */
  65 #define SR_ATU          (1 << 4)        /* Audio transmit FIFO underrun */
  66 #define SR_ARO          (1 << 5)        /* Audio receive FIFO overrun */
  67 #define SR_TTU          (1 << 6)        /* Telecom transmit FIFO underrun */
  68 #define SR_TRO          (1 << 7)        /* Telecom receive FIFO overrun */
  69 #define SR_ANF          (1 << 8)        /* Audio transmit FIFO not full */
  70 #define SR_ANE          (1 << 9)        /* Audio receive FIFO not empty */
  71 #define SR_TNF          (1 << 10)       /* Telecom transmit FIFO not full */
  72 #define SR_TNE          (1 << 11)       /* Telecom receive FIFO not empty */
  73 #define SR_CWC          (1 << 12)       /* Codec write completed */
  74 #define SR_CRC          (1 << 13)       /* Codec read completed */
  75 #define SR_ACE          (1 << 14)       /* Audio codec enabled */
  76 #define SR_TCE          (1 << 15)       /* Telecom codec enabled */
  77