1 /* $NetBSD: beccreg.h,v 1.1 2003/01/25 01:57:20 thorpej Exp $ */
4 * Copyright (c) 2002 Wasabi Systems, Inc.
7 * Written by Jason R. Thorpe for Wasabi Systems, Inc.
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed for the NetBSD Project by
20 * Wasabi Systems, Inc.
21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse
22 * or promote products derived from this software without specific prior
25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35 * POSSIBILITY OF SUCH DAMAGE.
42 * Register definitions for the ADI Engineering Big Endian Companion
43 * Chip for the Intel i80200.
48 #define BECC_REV_V7 0x00 /* rev <= 7 */
49 #define BECC_REV_V8 0x01 /* rev 8 */
50 #define BECC_REV_V9 0x02 /* rev >= 9 */
54 #define BECC_REG_BASE 0x04000000
55 #define BECC_REG_SIZE 0x01000000 /* 16M */
57 #define BECC_PCI_CONF_BASE 0x08000000
58 #define BECC_PCI_CONF_SIZE 0x02000000 /* 32M */
60 #define BECC_PCI_IO_BASE 0x0a000000
61 #define BECC_PCI_IO_SIZE 0x02000000 /* 32M */
63 #define BECC_PCI_MEM1_BASE 0x0c000000
64 #define BECC_PCI_MEM1_SIZE 0x02000000 /* 32M */
66 #define BECC_PCI_MEM2_BASE 0x0e000000
67 #define BECC_PCI_MEM2_SIZE 0x02000000 /* 32M */
69 #define BECC_SDRAM_BASE 0xc0000000
71 /* Peripheral clock is 33.3MHz */
72 #define BECC_PERIPH_CLOCK 33300000
74 /* BECC registers; offsets from BECC_REG_BASE */
76 #define BECC_PSISR 0x0000 /* PCI slave interrupt status */
77 #define PSISR_SERR (1U << 4) /* system error */
78 #define PSISR_PERR (1U << 9) /* parity error */
79 #define PSISR_IFU (1U << 16) /* inbound FIFO uflow */
80 #define PSISR_IFO (1U << 17) /* inbound FIFO oflow */
81 #define PSISR_OFU (1U << 18) /* outbound FIFO uflow */
82 #define PSISR_OFO (1U << 19) /* outbound FIFO oflow */
84 #define BECC_PSTR0 0x0010 /* PCI slave translation window #0 */
85 #define BECC_PSTR1 0x0018 /* PCI slave translation window #1 */
86 #define PSTRx_ADDRMASK (3U << 25) /* address mask */
87 #define PSTRx_BEE (1U << 0) /* big-endian enable */
88 #define BECC_PSTR2 0x0020 /* PCI slave translation window #2 */
89 #define PSTR2_ADDRMASK (0U) /* address mask (all SDRAM) */
91 #define BECC_PMISR 0x0100 /* PCI master interrupt status */
92 #define PMISR_PE (1U << 0) /* parity error */
93 #define PMISR_TA (1U << 2) /* target abort */
94 #define PMISR_MA (1U << 3) /* master abort */
95 #define PMISR_IFU (1U << 16) /* inbound FIFO uflow */
96 #define PMISR_IFO (1U << 17) /* inbound FIFO oflow */
97 #define PMISR_OFU (1U << 18) /* outbound FIFO uflow */
98 #define PMISR_OFO (1U << 19) /* outbound FIFO oflow */
100 #define BECC_IDSEL_BIT 11 /* first device on PCI bus */
102 #define BECC_POMR1 0x0110 /* PCI outbound memory window #1 */
103 #define BECC_POMR2 0x0114 /* PCI outbound memory window #2 */
104 #define POMRx_ADDRMASK 0xfe000000 /* address mask */
105 #define POMRx_BEE (1U << 2) /* big-endian enable */
106 #define POMRx_F32 (1U << 3) /* force 32-bit transfer */
107 #define POMRx_BO(x) (x) /* busrt order (MBZ) */
108 #define BECC_POMR3 0x0130 /* PCI outbound memory window #3 */
109 #define POMR3_ADDRMASK 0xc0000000 /* address mask */
111 #define BECC_POIR 0x0118 /* PCI outbound I/O window */
112 #define POIR_ADDRMASK 0xfe000000 /* address mask */
113 #define POIR_BEE (1U << 2) /* big-endian enable */
115 #define BECC_POCR 0x0120 /* PCI outbound config window */
116 #define POCR_BEE (1U << 2) /* big-endian enable */
117 #define POCR_TYPE (1U << 0) /* for type 1 cycles */
119 #define BECC_DMACR 0x0200 /* DMA control register */
120 #define DMACR_CE (1U << 0) /* channel enable */
122 #define BECC_DMASR 0x0204 /* DMA status register */
123 #define DMASR_PEF (1U << 0) /* PCI parity error */
124 #define DMASR_PTA (1U << 2) /* PCI target abort */
125 #define DMASR_PMA (1U << 3) /* PCI master abort */
126 #define DMASR_EOTI (1U << 8) /* end of transfer interrupt */
127 #define DMASR_CA (1U << 10) /* channel active */
128 #define DMASR_IFU (1U << 16) /* inbound FIFO uflow */
129 #define DMASR_IFO (1U << 17) /* inbound FIFO oflow */
130 #define DMASR_OFU (1U << 18) /* outbound FIFO uflow */
131 #define DMASR_OFO (1U << 19) /* outbound FIFO oflow */
133 #define BECC_DMAPCIAR 0x0210 /* DMA PCI address */
135 #define BECC_DMALAR 0x021c /* DMA local address */
137 #define BECC_DMABCR 0x0220 /* DMA byte count */
139 #define BECC_DMADCR 0x0224 /* DMA descriptor control */
140 #define DMADCR_F32 (1U << 6) /* force 32-bit */
141 #define DMADCR_BEE (1U << 5) /* big-endian enable */
142 #define DMADCR_PCICMD(x) (x) /* PCI command */
144 #define PCICMD_MR 0x6 /* memory read */
145 #define PCICMD_MRL 0xe /* memory read line */
146 #define PCICMD_MRM 0xc /* memory read multiple */
147 #define PCICMD_MW 0x7 /* memory write */
149 #define BECC_TSCRA 0x0300 /* Timer status/control A */
150 #define BECC_TSCRB 0x0320 /* Timer status/control B */
151 #define TSCRx_TE (1U << 0) /* timer enable */
152 #define TSCRx_CM (1U << 1) /* continuous mode */
153 #define TSCRx_TIF (1U << 9) /* timer interrupt flag */
155 #define BECC_TPRA 0x0304 /* Timer preload A */
156 #define BECC_TPRB 0x0324 /* Timer preload B */
158 #define BECC_TCVRA 0x0308 /* Timer current value A */
159 #define BECC_TCVRB 0x0328 /* Timer current value B */
161 #define BECC_ICSR 0x0400 /* Interrupt control/status */
162 #define BECC_ICMR 0x0404 /* Interrupt mask */
163 #define BECC_ICSTR 0x0408 /* Interrupt steer */
165 #define ICU_SOFT 0 /* software interrupt */
166 #define ICU_TIMERA 1 /* timer A */
167 #define ICU_TIMERB 2 /* timer B */
168 #define ICU_DIAGERR 7 /* diagnostic error */
169 #define ICU_DMA_EOT 8 /* DMA end-of-transfer */
170 #define ICU_DMA_PEF 9 /* DMA parity error */
171 #define ICU_DMA_TA 10 /* DMA target abort */
172 #define ICU_DMA_MA 11 /* DMA master abort */
173 #define ICU_PCI_PERR 16 /* PCI parity error */
174 #define ICU_PCI_SERR 19 /* PCI system error */
175 #define ICU_PCI_POAPEI 20 /* PCI outbound ATU parity error */
176 #define ICU_PCI_POATAI 21 /* PCI outbound ATU target abort */
177 #define ICU_PCI_POAMAI 22 /* PCI outbound ATU master abort */
178 #define ICU_UARTA 24 /* UART A */
179 #define ICU_UARTB 25 /* UART B */
180 #define ICU_PCI_INTA 26 /* PCI INTA# */
181 #define ICU_PCI_INTB 27 /* PCI INTB# */
182 #define ICU_PCI_INTC 28 /* PCI INTC# */
183 #define ICU_PCI_INTD 29 /* PCI INTD# */
184 #define ICU_PUSHBUTTON 30 /* push button pulse */
186 #define ICU_RESERVED_MASK ((1U << 3) | (1U << 4) | (1U << 5) | \
187 (1U << 6) | (1U << 12) | (1U << 13) | \
188 (1U << 14) | (1U << 15) | (1U << 17) | \
189 (1U << 18) | (1U << 23) | (1U << 31))
190 #define ICU_VALID_MASK (~ICU_RESERVED_MASK)
192 #define BECC_RSSR 0x0500 /* rotary switch status */
193 #define RSSR_POS 0x0000000f /* switch position */
194 #define RSSR_BE (1U << 6) /* big-endian jumper */
196 #endif /* _BECCREG_H_ */
