sys/arch/arm/xscale/i80321var.h

   1 /*      $NetBSD$        */
   2
   3 /*
   4  * Copyright (c) 2002, 2003 Wasabi Systems, Inc.
   5  * All rights reserved.
   6  *
   7  * Written by Jason R. Thorpe for Wasabi Systems, Inc.
   8  *
   9  * Redistribution and use in source and binary forms, with or without
  10  * modification, are permitted provided that the following conditions
  11  * are met:
  12  * 1. Redistributions of source code must retain the above copyright
  13  *    notice, this list of conditions and the following disclaimer.
  14  * 2. Redistributions in binary form must reproduce the above copyright
  15  *    notice, this list of conditions and the following disclaimer in the
  16  *    documentation and/or other materials provided with the distribution.
  17  * 3. All advertising materials mentioning features or use of this software
  18  *    must display the following acknowledgement:
  19  *      This product includes software developed for the NetBSD Project by
  20  *      Wasabi Systems, Inc.
  21  * 4. The name of Wasabi Systems, Inc. may not be used to endorse
  22  *    or promote products derived from this software without specific prior
  23  *    written permission.
  24  *
  25  * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
  26  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  27  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  28  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
  29  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  30  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  31  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  32  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  33  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  34  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  35  * POSSIBILITY OF SUCH DAMAGE.
  36  */
  37
  38 #ifndef _ARM_XSCALE_I80321VAR_H_
  39 #define _ARM_XSCALE_I80321VAR_H_
  40
  41 #include <sys/queue.h>
  42 #include <dev/pci/pcivar.h>
  43
  44 /*
  45  * There are roughly 32 interrupt sources.
  46  */
  47 #define NIRQ            32
  48
  49 struct intrhand {
  50         TAILQ_ENTRY(intrhand) ih_list;  /* link on intrq list */
  51         int (*ih_func)(void *);         /* handler */
  52         void *ih_arg;                   /* arg for handler */
  53         int ih_ipl;                     /* IPL_* */
  54         int ih_irq;                     /* IRQ number */
  55 };
  56
  57 #define IRQNAMESIZE     sizeof("iop321 irq 31")
  58
  59 struct intrq {
  60         TAILQ_HEAD(, intrhand) iq_list; /* handler list */
  61         struct evcnt iq_ev;             /* event counter */
  62         int iq_mask;                    /* IRQs to mask while handling */
  63         int iq_levels;                  /* IPL_*'s this IRQ has */
  64         int iq_ist;                     /* share type */
  65 };
  66
  67 struct i80321_softc {
  68         struct device sc_dev;           /* generic device glue */
  69
  70         int sc_is_host;                 /* indicates if we're a host or
  71                                            plugged into another host */
  72
  73         /*
  74          * This is the bus_space and handle used to access the
  75          * i80321 itself.  This is filled in by the board-specific
  76          * front-end.
  77          */
  78         bus_space_tag_t sc_st;
  79         bus_space_handle_t sc_sh;
  80
  81         /* Handles for the various subregions. */
  82         bus_space_handle_t sc_atu_sh;
  83         bus_space_handle_t sc_mcu_sh;
  84
  85         /*
  86          * We expect the board-specific front-end to have already mapped
  87          * the PCI I/O space .. it is only 64K, and I/O mappings tend to
  88          * be smaller than a page size, so it's generally more efficient
  89          * to map them all into virtual space in one fell swoop.
  90          */
  91         vaddr_t sc_iow_vaddr;           /* I/O window vaddr */
  92
  93         /*
  94          * Variables that define the Inbound windows.  The base address of
  95          * 0-2 are configured by a host via BARs.  The xlate variable
  96          * defines the start of the local address space that it maps to.
  97          * The size variable defines the byte size.
  98          *
  99          * The first 3 windows are for incoming PCI memory read/write
 100          * cycles from a host.  The 4th window, not configured by the
 101          * host (as it outside the normal BAR range) is the inbound
 102          * window for PCI devices controlled by the i80321.
 103          */
 104         struct {
 105                 uint32_t iwin_base_hi;
 106                 uint32_t iwin_base_lo;
 107                 uint32_t iwin_xlate;
 108                 uint32_t iwin_size;
 109         } sc_iwin[4];
 110
 111         /*
 112          * Variables that define the Outbound windows.
 113          */
 114         struct {
 115                 uint32_t owin_xlate_lo;
 116                 uint32_t owin_xlate_hi;
 117         } sc_owin[2];
 118
 119         /*
 120          * This is the PCI address that the Outbound I/O window maps to.
 121          * The offset is to keep the actual used I/O address away from 0,
 122          * which can be bad if, say, an i8254x gig-e chip gets mapped there.
 123          * The 0 value apparently looks like "unconfigured" to the controller
 124          * and it ignores writes to that region (it doesn't cause a bus fault,
 125          * it just ignores them--leading to a non-functional controller).  The
 126          * wm(4) driver usually uses memory-mapped regions, but does use the
 127          * I/O-mapped region for reset operations in order to work around a
 128          * bug in the chip.
 129          * Iyonix, while using sc_ioout_xlate 0 needs an offset of 0, too, in
 130          * order to function properly.  These values are both set in the
 131          * port-specific i80321_mainbus_attach() routine.
 132          */
 133         uint32_t sc_ioout_xlate;
 134         uint32_t sc_ioout_xlate_offset;
 135
 136         /* Bus space, DMA, and PCI tags for the PCI bus (private devices). */
 137         struct bus_space sc_pci_iot;
 138         struct bus_space sc_pci_memt;
 139         struct arm32_bus_dma_tag sc_pci_dmat;
 140         struct arm32_pci_chipset sc_pci_chipset;
 141
 142         /* DMA window info for PCI DMA. */
 143         struct arm32_dma_range sc_pci_dma_range;
 144
 145         /* GPIO state */
 146         uint8_t sc_gpio_dir;    /* GPIO pin direction (1 == output) */
 147         uint8_t sc_gpio_val;    /* GPIO output pin value */
 148
 149         /* DMA tag for local devices. */
 150         struct arm32_bus_dma_tag sc_local_dmat;
 151 };
 152
 153 /*
 154  * Arguments used to attach IOP built-ins.
 155  */
 156 struct iopxs_attach_args {
 157         const char *ia_name;    /* name of device */
 158         bus_space_tag_t ia_st;  /* space tag */
 159         bus_space_handle_t ia_sh;/* handle of IOP base */
 160         bus_dma_tag_t ia_dmat;  /* DMA tag */
 161         bus_addr_t ia_offset;   /* offset of device from IOP base */
 162         bus_size_t ia_size;     /* size of sub-device */
 163 };
 164
 165 extern struct bus_space i80321_bs_tag;
 166 extern struct i80321_softc *i80321_softc;
 167 extern const char * const i80321_irqnames[];
 168
 169 extern void (*i80321_hardclock_hook)(void);
 170
 171 void    i80321_sdram_bounds(bus_space_tag_t, bus_space_handle_t,
 172             paddr_t *, psize_t *);
 173
 174 void    i80321_calibrate_delay(void);
 175
 176 void    i80321_icu_init(void);
 177 void    i80321_intr_init(void);
 178 void    *i80321_intr_establish(int, int, int (*)(void *), void *);
 179 void    i80321_intr_disestablish(void *);
 180
 181 void    i80321_gpio_set_direction(uint8_t, uint8_t);
 182 void    i80321_gpio_set_val(uint8_t, uint8_t);
 183 uint8_t i80321_gpio_get_val(void);
 184
 185 void    i80321_bs_init(bus_space_tag_t, void *);
 186 void    i80321_io_bs_init(bus_space_tag_t, void *);
 187 void    i80321_mem_bs_init(bus_space_tag_t, void *);
 188
 189 void    i80321_local_dma_init(struct i80321_softc *sc);
 190
 191 void    i80321_pci_init(pci_chipset_tag_t, void *);
 192
 193 void    i80321_attach(struct i80321_softc *);
 194
 195 #endif /* _ARM_XSCALE_I80321VAR_H_ */