sys/arch/arm/xscale/ixp425_if_npereg.h

   1 /*      $NetBSD: ixp425_if_npereg.h,v 1.2 2009/03/11 11:36:33 msaitoh Exp $     */
   2
   3 /*-
   4  * Copyright (c) 2006 Sam Leffler, Errno Consulting
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer,
  12  *    without modification.
  13  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
  14  *    similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
  15  *    redistribution must be conditioned upon including a substantially
  16  *    similar Disclaimer requirement for further binary redistribution.
  17  *
  18  * NO WARRANTY
  19  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  20  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  21  * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
  22  * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
  23  * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
  24  * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
  27  * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  29  * THE POSSIBILITY OF SUCH DAMAGES.
  30  *
  31  * $FreeBSD: src/sys/arm/xscale/ixp425/if_npereg.h,v 1.1 2006/11/19 23:55:23 sam Exp $
  32  */
  33
  34 /*
  35  * Copyright (c) 2001-2005, Intel Corporation.
  36  * All rights reserved.
  37  *
  38  * Redistribution and use in source and binary forms, with or without
  39  * modification, are permitted provided that the following conditions
  40  * are met:
  41  * 1. Redistributions of source code must retain the above copyright
  42  *    notice, this list of conditions and the following disclaimer.
  43  * 2. Redistributions in binary form must reproduce the above copyright
  44  *    notice, this list of conditions and the following disclaimer in the
  45  *    documentation and/or other materials provided with the distribution.
  46  * 3. Neither the name of the Intel Corporation nor the names of its contributors
  47  *    may be used to endorse or promote products derived from this software
  48  *    without specific prior written permission.
  49  *
  50  *
  51  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
  52  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  53  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  54  * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
  55  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  56  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  57  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  58  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  59  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  60  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  61  * SUCH DAMAGE.
  62  */
  63
  64 #ifndef ARM_XSCALE_IF_NPEREG_H
  65 #define ARM_XSCALE_IF_NPEREG_H
  66
  67 /*
  68  * NPE/NPE tx/rx descriptor format.  This is just the area
  69  * shared with ucode running in the NPE; the driver-specific
  70  * state is defined in the driver.  The shared area must be
  71  * cacheline-aligned.  We allocate NPE_MAXSEG "descriptors"
  72  * per buffer; this allows us to do minimal s/g.  The number
  73  * of descriptors can be expanded but doing so uses memory
  74  * so should be done with care.
  75  *
  76  * The driver sets up buffers in uncached memory.
  77  */
  78 #define NPE_MAXSEG      3               /* empirically selected */
  79
  80 struct npehwbuf {
  81         struct {                        /* NPE shared area, cacheline aligned */
  82                 uint32_t next;          /* phys addr of next segment */
  83                 uint32_t len;           /* buffer/segment length (bytes) */
  84                 uint32_t data;          /* phys addr of data segment */
  85                 uint32_t pad[5];        /* pad to cacheline */
  86         } ix_ne[NPE_MAXSEG];
  87 };
  88
  89 /* NPE ID's */
  90 #define NPE_A           0
  91 #define NPE_B           1
  92 #define NPE_C           2
  93 #define NPE_MAX         (NPE_C+1)
  94
  95 #define NPE_PORTS_MAX           2       /* logical ports */
  96 #define NPE_FRAME_SIZE_DEFAULT  1536
  97 #define NPE_FRAME_SIZE_MAX      (65536-64)
  98 #define NPE_FRAME_SIZE_MIN      64
  99
 100 /*
 101  * Queue Manager-related definitions.
 102  *
 103  * These define the layout of 32-bit Q entries passed
 104  * between the host cpu and the NPE's.
 105  */
 106 #define NPE_QM_Q_NPE(e)         (((e)>>0)&0x3)          /* NPE ID */
 107 #define NPE_QM_Q_PORT(e)        (((e)>>3)&0x1)          /* Port ID */
 108 #define NPE_QM_Q_PRIO(e)        (((e)>>0)&0x3)          /* 802.1d priority */
 109 #define NPE_QM_Q_ADDR(e)        ((e)&0xffffffe0u)       /* phys address */
 110
 111 /*
 112  * Host->NPE requests written to the shared mailbox.
 113  * The NPE writes the same value back as an ACK.
 114  */
 115 #define NPE_GETSTATUS           0x00    /* get firmware revision */
 116 #define NPE_SETPORTADDRESS      0x01    /* set port id and mac address */
 117 #define NPE_GETMACADDRDB        0x02    /* upload filter database */
 118 #define NPE_SETMACADDRDB        0x03    /* download filter database */
 119 #define NPE_GETSTATS            0x04    /* get statistics */
 120 #define NPE_RESETSTATS          0x05    /* reset stats + return result */
 121 #define NPE_SETMAXFRAME         0x06    /* configure max tx/rx frame lengths */
 122 #define NPE_SETRXTAGMODE        0x07    /* configure VLAN rx operating mode */
 123 #define NPE_SETDEFRXVID         0x08    /* set def VLAN tag + traffic class */
 124 #define NPE_SETRXQOSENTRY       0x0b    /* map user pri -> QoS class+rx qid */
 125 #define NPE_SETFIREWALLMODE     0x0e    /* config firewall services */
 126 #define NPE_SETLOOPBACK         0x12    /* enable/disable loopback */
 127 #define NPE_ADDRESSFILTERCONFIG 0x14    /* update multicast filter */
 128 #define NPE_NOTIFYMACRECOVERYDONE 0x16  /* MAC has been recovered */
 129 #define NPE_MACRECOVERYSTART    0x17    /* message from NPE to recover MAC*/
 130 /* ... XXX more */
 131
 132 #define NPE_MAC_MSGID_SHL       24
 133 #define NPE_MAC_PORTID_SHL      16
 134
 135 /*
 136  * MAC register definitions; see section
 137  * 15.2 of the Intel Developers Manual.
 138  */
 139 #define NPE_MAC_TX_CNTRL1       0x000
 140 #define NPE_MAC_TX_CNTRL2       0x004
 141 #define NPE_MAC_RX_CNTRL1       0x010
 142 #define NPE_MAC_RX_CNTRL2       0x014
 143 #define NPE_MAC_RANDOM_SEED     0x020
 144 #define NPE_MAC_THRESH_P_EMPTY  0x030
 145 #define NPE_MAC_THRESH_P_FULL   0x038
 146 #define NPE_MAC_BUF_SIZE_TX     0x040
 147 #define NPE_MAC_TX_DEFER        0x050
 148 #define NPE_MAC_RX_DEFER        0x054
 149 #define NPE_MAC_TX_TWO_DEFER_1  0x060
 150 #define NPE_MAC_TX_TWO_DEFER_2  0x064
 151 #define NPE_MAC_SLOT_TIME       0x070
 152 #define NPE_MAC_MDIO_CMD_1      0x080
 153 #define NPE_MAC_MDIO_CMD_2      0x084
 154 #define NPE_MAC_MDIO_CMD_3      0x088
 155 #define NPE_MAC_MDIO_CMD_4      0x08c
 156 #define NPE_MAC_MDIO_STS_1      0x090
 157 #define NPE_MAC_MDIO_STS_2      0x094
 158 #define NPE_MAC_MDIO_STS_3      0x098
 159 #define NPE_MAC_MDIO_STS_4      0x09c
 160 #define NPE_MAC_ADDR_MASK_1     0x0A0
 161 #define NPE_MAC_ADDR_MASK_2     0x0A4
 162 #define NPE_MAC_ADDR_MASK_3     0x0A8
 163 #define NPE_MAC_ADDR_MASK_4     0x0AC
 164 #define NPE_MAC_ADDR_MASK_5     0x0B0
 165 #define NPE_MAC_ADDR_MASK_6     0x0B4
 166 #define NPE_MAC_ADDR_1          0x0C0
 167 #define NPE_MAC_ADDR_2          0x0C4
 168 #define NPE_MAC_ADDR_3          0x0C8
 169 #define NPE_MAC_ADDR_4          0x0CC
 170 #define NPE_MAC_ADDR_5          0x0D0
 171 #define NPE_MAC_ADDR_6          0x0D4
 172 #define NPE_MAC_INT_CLK_THRESH  0x0E0
 173 #define NPE_MAC_UNI_ADDR_1      0x0F0
 174 #define NPE_MAC_UNI_ADDR_2      0x0F4
 175 #define NPE_MAC_UNI_ADDR_3      0x0F8
 176 #define NPE_MAC_UNI_ADDR_4      0x0FC
 177 #define NPE_MAC_UNI_ADDR_5      0x100
 178 #define NPE_MAC_UNI_ADDR_6      0x104
 179 #define NPE_MAC_CORE_CNTRL      0x1FC
 180
 181 #define NPE_MAC_ADDR_MASK(i)    (NPE_MAC_ADDR_MASK_1 + ((i)<<2))
 182 #define NPE_MAC_ADDR(i)         (NPE_MAC_ADDR_1 + ((i)<<2))
 183 #define NPE_MAC_UNI_ADDR(i)     (NPE_MAC_UNI_ADDR_1 + ((i)<<2))
 184
 185 /*
 186  * Bit definitions
 187  */
 188
 189 /* TX Control Register 1*/
 190 #define NPE_TX_CNTRL1_TX_EN             0x01    /* enable TX engine */
 191 #define NPE_TX_CNTRL1_DUPLEX            0x02    /* select half duplex */
 192 #define NPE_TX_CNTRL1_RETRY             0x04    /* auto-retry on collision */
 193 #define NPE_TX_CNTRL1_PAD_EN            0x08    /* pad frames <64 bytes */
 194 #define NPE_TX_CNTRL1_FCS_EN            0x10    /* append FCS */
 195 #define NPE_TX_CNTRL1_2DEFER            0x20    /* select 2-part deferral */
 196 #define NPE_TX_CNTRL1_RMII              0x40
 197
 198 /* TX Control Register 2 */
 199 #define NPE_TX_CNTRL2_RETRIES_MASK      0xf     /* max retry count */
 200
 201 /* RX Control Register 1 */
 202 #define NPE_RX_CNTRL1_RX_EN             0x01    /* enable RX engine */
 203 #define NPE_RX_CNTRL1_PADSTRIP_EN       0x02    /* strip frame padding */
 204 #define NPE_RX_CNTRL1_CRC_EN            0x04    /* include CRC in RX frame */
 205 #define NPE_RX_CNTRL1_PAUSE_EN          0x08    /* detect Pause frames */
 206 #define NPE_RX_CNTRL1_LOOP_EN           0x10    /* loopback tx/rx */
 207 #define NPE_RX_CNTRL1_ADDR_FLTR_EN      0x20    /* enable address filtering */
 208 #define NPE_RX_CNTRL1_RX_RUNT_EN        0x40    /* enable RX of runt frames */
 209 #define NPE_RX_CNTRL1_BCAST_DIS         0x80    /* discard broadcast frames */
 210
 211 /* RX Control Register 2 */
 212 #define NPE_RX_CNTRL2_DEFER_EN  0x01
 213
 214 /* Core Control Register */
 215 #define NPE_CORE_RESET                  0x01    /* MAC reset state */
 216 #define NPE_CORE_RX_FIFO_FLUSH          0x02    /* flush RX FIFO */
 217 #define NPE_CORE_TX_FIFO_FLUSH          0x04    /* flush TX FIFO */
 218 #define NPE_CORE_SEND_JAM               0x08    /* send JAM on packet RX */
 219 #define NPE_CORE_MDC_EN                 0x10    /* IXP42X drives MDC clock */
 220
 221 /*
 222  * Stat block returned by NPE with NPE_GETSTATS msg.
 223  */
 224 struct npestats {
 225         uint32_t dot3StatsAlignmentErrors;
 226         uint32_t dot3StatsFCSErrors;
 227         uint32_t dot3StatsInternalMacReceiveErrors;
 228         uint32_t RxOverrunDiscards;
 229         uint32_t RxLearnedEntryDiscards;
 230         uint32_t RxLargeFramesDiscards;
 231         uint32_t RxSTPBlockedDiscards;
 232         uint32_t RxVLANTypeFilterDiscards;
 233         uint32_t RxVLANIdFilterDiscards;
 234         uint32_t RxInvalidSourceDiscards;
 235         uint32_t RxBlackListDiscards;
 236         uint32_t RxWhiteListDiscards;
 237         uint32_t RxUnderflowEntryDiscards;
 238         uint32_t dot3StatsSingleCollisionFrames;
 239         uint32_t dot3StatsMultipleCollisionFrames;
 240         uint32_t dot3StatsDeferredTransmissions;
 241         uint32_t dot3StatsLateCollisions;
 242         uint32_t dot3StatsExcessiveCollisions;
 243         uint32_t dot3StatsInternalMacTransmitErrors;
 244         uint32_t dot3StatsCarrierSenseErrors;
 245         uint32_t TxLargeFrameDiscards;
 246         uint32_t TxVLANIdFilterDiscards;
 247 };
 248
 249 /*
 250  * Default values
 251  */
 252 #define NPE_MAC_INT_CLK_THRESH_DEFAULT  0x1
 253
 254 #define NPE_MAC_RESET_DELAY    1
 255
 256 /* Slot time */
 257 #define NPE_MAC_SLOT_TIME_MII_DEFAULT   0x80
 258 #define NPE_MAC_SLOT_TIME_RMII_DEFAULT  0xFF
 259
 260 /* TX fifo threshold */
 261 #define NPE_MAC_BUF_SIZE_TX_DEFAULT     0x18    /* CSR 2 or higher */
 262
 263 /*
 264  * MII definitions - these have been verified against the LXT971 and LXT972 PHYs
 265  */
 266 #define NPE_MII_REG_SHL         16
 267 #define NPE_MII_ADDR_SHL        21
 268
 269 /* NB: shorthands for mii bus mdio routines */
 270 #define NPE_MAC_MDIO_CMD        NPE_MAC_MDIO_CMD_1
 271 #define NPE_MAC_MDIO_STS        NPE_MAC_MDIO_STS_1
 272
 273 #define NPE_MII_GO                  (1<<31)
 274 #define NPE_MII_WRITE               (1<<26)
 275 #define NPE_MII_TIMEOUT_10TH_SECS        5
 276 #define NPE_MII_10TH_SEC_IN_MILLIS     100
 277 #define NPE_MII_READ_FAIL           (1<<31)
 278
 279 #define NPE_MII_PHY_DEF_DELAY   300     /* max delay before link up, etc. */
 280 #define NPE_MII_PHY_NO_DELAY    0x0     /* do not delay */
 281 #define NPE_MII_PHY_NULL        0xff    /* PHY is not present */
 282 #define NPE_MII_PHY_DEF_ADDR    0x0     /* default PHY's logical address */
 283
 284 /* Register definition */
 285 #define NPE_MII_CTRL_REG        0x0     /* Control Register */
 286 #define NPE_MII_STAT_REG        0x1     /* Status Register */
 287 #define NPE_MII_PHY_ID1_REG     0x2     /* PHY identifier 1 Register */
 288 #define NPE_MII_PHY_ID2_REG     0x3     /* PHY identifier 2 Register */
 289 #define NPE_MII_AN_ADS_REG      0x4     /* Auto-Negotiation       */
 290                                         /* Advertisement Register */
 291 #define NPE_MII_AN_PRTN_REG     0x5     /* Auto-Negotiation         */
 292                                         /* partner ability Register */
 293 #define NPE_MII_AN_EXP_REG      0x6     /* Auto-Negotiation   */
 294                                         /* Expansion Register */
 295 #define NPE_MII_AN_NEXT_REG     0x7     /* Auto-Negotiation            */
 296                                         /* next-page transmit Register */
 297 #endif /* ARM_XSCALE_IF_NPEREG_H */