sys/arch/arm/xscale/pxa2x0_intr.c

   1 /*      $NetBSD: pxa2x0_intr.c,v 1.15 2008/11/07 16:14:37 rafal Exp $   */
   2
   3 /*
   4  * Copyright (c) 2002  Genetec Corporation.  All rights reserved.
   5  * Written by Hiroyuki Bessho for Genetec Corporation.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  * 3. All advertising materials mentioning features or use of this software
  16  *    must display the following acknowledgement:
  17  *      This product includes software developed for the NetBSD Project by
  18  *      Genetec Corporation.
  19  * 4. The name of Genetec Corporation may not be used to endorse or
  20  *    promote products derived from this software without specific prior
  21  *    written permission.
  22  *
  23  * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND
  24  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  25  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  26  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL GENETEC CORPORATION
  27  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  28  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  29  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  30  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  31  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  32  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  33  * POSSIBILITY OF SUCH DAMAGE.
  34  */
  35
  36 /*
  37  * IRQ handler for the Intel PXA2X0 processor.
  38  * It has integrated interrupt controller.
  39  */
  40
  41 #include <sys/cdefs.h>
  42 __KERNEL_RCSID(0, "$NetBSD: pxa2x0_intr.c,v 1.15 2008/11/07 16:14:37 rafal Exp $");
  43
  44 #include <sys/param.h>
  45 #include <sys/systm.h>
  46 #include <sys/malloc.h>
  47
  48 #include <machine/bus.h>
  49 #include <machine/intr.h>
  50 #include <machine/lock.h>
  51
  52 #include <arm/xscale/pxa2x0cpu.h>
  53 #include <arm/xscale/pxa2x0reg.h>
  54 #include <arm/xscale/pxa2x0var.h>
  55 #include <arm/xscale/pxa2x0_intr.h>
  56 #include <arm/sa11x0/sa11x0_var.h>
  57
  58 /*
  59  * INTC autoconf glue
  60  */
  61 static int      pxaintc_match(struct device *, struct cfdata *, void *);
  62 static void     pxaintc_attach(struct device *, struct device *, void *);
  63
  64 CFATTACH_DECL(pxaintc, sizeof(struct device),
  65     pxaintc_match, pxaintc_attach, NULL, NULL);
  66
  67 static int pxaintc_attached;
  68
  69 static int stray_interrupt(void *);
  70 static void init_interrupt_masks(void);
  71
  72 /*
  73  * interrupt dispatch table.
  74  */
  75 #ifdef MULTIPLE_HANDLERS_ON_ONE_IRQ
  76 struct intrhand {
  77         TAILQ_ENTRY(intrhand) ih_list;  /* link on intrq list */
  78         int (*ih_func)(void *);         /* handler */
  79         void *ih_arg;                   /* arg for handler */
  80 };
  81 #endif
  82
  83 static struct intrhandler {
  84 #ifdef MULTIPLE_HANDLERS_ON_ONE_IRQ
  85         TAILQ_HEAD(,intrhand) list;
  86 #else
  87         pxa2x0_irq_handler_t func;
  88 #endif
  89         void *cookie;           /* NULL for stackframe */
  90         /* struct evbnt ev; */
  91 } handler[ICU_LEN];
  92
  93 volatile int softint_pending;
  94 volatile int intr_mask;
  95 /* interrupt masks for each level */
  96 int pxa2x0_imask[NIPL];
  97 static int extirq_level[ICU_LEN];
  98
  99
 100 static int
 101 pxaintc_match(struct device *parent, struct cfdata *cf, void *aux)
 102 {
 103         struct pxaip_attach_args *pxa = aux;
 104
 105         if (pxaintc_attached || pxa->pxa_addr != PXA2X0_INTCTL_BASE)
 106                 return (0);
 107
 108         return (1);
 109 }
 110
 111 void
 112 pxaintc_attach(struct device *parent, struct device *self, void *args)
 113 {
 114         int i;
 115
 116         pxaintc_attached = 1;
 117
 118         aprint_normal(": Interrupt Controller\n");
 119
 120 #define SAIPIC_ICCR     0x14
 121
 122         write_icu(SAIPIC_ICCR, 1);
 123         write_icu(SAIPIC_MR, 0);
 124
 125         for(i = 0; i < sizeof handler / sizeof handler[0]; ++i){
 126                 handler[i].func = stray_interrupt;
 127                 handler[i].cookie = (void *)(intptr_t) i;
 128                 extirq_level[i] = IPL_SERIAL;
 129         }
 130
 131         init_interrupt_masks();
 132
 133         _splraise(IPL_SERIAL);
 134         enable_interrupts(I32_bit);
 135 }
 136
 137 /*
 138  * Invoked very early on from the board-specific initarm(), in order to
 139  * inform us the virtual address of the interrupt controller's registers.
 140  */
 141 void
 142 pxa2x0_intr_bootstrap(vaddr_t addr)
 143 {
 144
 145         pxaic_base = addr;
 146 }
 147
 148 static inline void
 149 __raise(int ipl)
 150 {
 151
 152         if (curcpu()->ci_cpl < ipl)
 153                 pxa2x0_setipl(ipl);
 154 }
 155
 156 /*
 157  * called from irq_entry.
 158  */
 159 void
 160 pxa2x0_irq_handler(void *arg)
 161 {
 162         struct clockframe *frame = arg;
 163         uint32_t irqbits;
 164         int irqno;
 165         int saved_spl_level;
 166
 167         saved_spl_level = curcpu()->ci_cpl;
 168
 169         /* get pending IRQs */
 170         irqbits = read_icu(SAIPIC_IP);
 171
 172         while ((irqno = find_first_bit(irqbits)) >= 0) {
 173                 /* XXX: Shuould we handle IRQs in priority order? */
 174
 175                 /* raise spl to stop interrupts of lower priorities */
 176                 if (saved_spl_level < extirq_level[irqno])
 177                         pxa2x0_setipl(extirq_level[irqno]);
 178
 179 #ifdef notyet
 180                 /* Enable interrupt */
 181 #endif
 182 #ifndef MULTIPLE_HANDLERS_ON_ONE_IRQ
 183                 (* handler[irqno].func)(
 184                         handler[irqno].cookie == 0
 185                         ? frame : handler[irqno].cookie );
 186 #else
 187                 /* process all handlers for this interrupt.
 188                    XXX not yet */
 189 #endif
 190
 191 #ifdef notyet
 192                 /* Disable interrupt */
 193 #endif
 194
 195                 irqbits &= ~(1<<irqno);
 196         }
 197
 198         /* restore spl to that was when this interrupt happen */
 199         pxa2x0_setipl(saved_spl_level);
 200
 201 #ifdef __HAVE_FAST_SOFTINTS
 202         cpu_dosoftints();
 203 #endif
 204 }
 205
 206 static int
 207 stray_interrupt(void *cookie)
 208 {
 209         int irqno = (int)cookie;
 210         int irqmin = CPU_IS_PXA250 ? PXA250_IRQ_MIN : PXA270_IRQ_MIN;
 211
 212         printf("stray interrupt %d\n", irqno);
 213
 214         if (irqmin <= irqno && irqno < ICU_LEN){
 215                 int save = disable_interrupts(I32_bit);
 216                 write_icu(SAIPIC_MR,
 217                     read_icu(SAIPIC_MR) & ~(1U<<irqno));
 218                 restore_interrupts(save);
 219         }
 220
 221         return 0;
 222 }
 223
 224
 225
 226 /*
 227  * Interrupt Mask Handling
 228  */
 229
 230 void
 231 pxa2x0_update_intr_masks(int irqno, int level)
 232 {
 233         int mask = 1U<<irqno;
 234         int psw = disable_interrupts(I32_bit);
 235         int i;
 236
 237         for(i = 0; i < level; ++i)
 238                 pxa2x0_imask[i] |= mask; /* Enable interrupt at lower level */
 239
 240         for( ; i < NIPL-1; ++i)
 241                 pxa2x0_imask[i] &= ~mask; /* Disable itnerrupt at upper level */
 242
 243         /*
 244          * Enforce a hierarchy that gives "slow" device (or devices with
 245          * limited input buffer space/"real-time" requirements) a better
 246          * chance at not dropping data.
 247          */
 248         pxa2x0_imask[IPL_SOFTBIO] &= pxa2x0_imask[IPL_SOFTCLOCK];
 249         pxa2x0_imask[IPL_SOFTNET] &= pxa2x0_imask[IPL_SOFTBIO];
 250         pxa2x0_imask[IPL_SOFTSERIAL] &= pxa2x0_imask[IPL_SOFTNET];
 251         pxa2x0_imask[IPL_VM] &= pxa2x0_imask[IPL_SOFTSERIAL];
 252         pxa2x0_imask[IPL_SCHED] &= pxa2x0_imask[IPL_VM];
 253         pxa2x0_imask[IPL_HIGH] &= pxa2x0_imask[IPL_SCHED];
 254
 255         write_icu(SAIPIC_MR, pxa2x0_imask[curcpu()->ci_cpl]);
 256
 257         restore_interrupts(psw);
 258 }
 259
 260
 261 static void
 262 init_interrupt_masks(void)
 263 {
 264
 265         /*
 266          * disable all interrups until handlers are installed.
 267          */
 268         memset(pxa2x0_imask, 0, sizeof(pxa2x0_imask));
 269
 270 }
 271
 272 #undef splx
 273 void
 274 splx(int ipl)
 275 {
 276         pxa2x0_splx(ipl);
 277 }
 278
 279 #undef _splraise
 280 int
 281 _splraise(int ipl)
 282 {
 283         return pxa2x0_splraise(ipl);
 284 }
 285
 286 #undef _spllower
 287 int
 288 _spllower(int ipl)
 289 {
 290         return pxa2x0_spllower(ipl);
 291 }
 292
 293 void *
 294 pxa2x0_intr_establish(int irqno, int level,
 295     int (*func)(void *), void *cookie)
 296 {
 297         int psw;
 298         int irqmin = CPU_IS_PXA250 ? PXA250_IRQ_MIN : PXA270_IRQ_MIN;
 299
 300         if (irqno < irqmin || irqno >= ICU_LEN)
 301                 panic("intr_establish: bogus irq number %d", irqno);
 302
 303         psw = disable_interrupts(I32_bit);
 304
 305         handler[irqno].cookie = cookie;
 306         handler[irqno].func = func;
 307         extirq_level[irqno] = level;
 308         pxa2x0_update_intr_masks(irqno, level);
 309
 310         intr_mask = pxa2x0_imask[curcpu()->ci_cpl];
 311
 312         restore_interrupts(psw);
 313
 314         return (&handler[irqno]);
 315 }
 316
 317 void
 318 pxa2x0_intr_disestablish(void *cookie)
 319 {
 320         struct intrhandler *lhandler = cookie, *ih;
 321         int irqmin = CPU_IS_PXA250 ? PXA250_IRQ_MIN : PXA270_IRQ_MIN;
 322         int irqno = lhandler - handler;
 323         int psw;
 324
 325         if (irqno < irqmin || irqno >= ICU_LEN)
 326                 panic("intr_disestablish: bogus irq number %d", irqno);
 327
 328         psw = disable_interrupts(I32_bit);
 329
 330         ih = &handler[irqno];
 331         ih->func = stray_interrupt;
 332         ih->cookie = (void *)(intptr_t)irqno;
 333         extirq_level[irqno] = IPL_SERIAL;
 334         pxa2x0_update_intr_masks(irqno, IPL_SERIAL);
 335
 336         restore_interrupts(psw);
 337 }
 338
 339 /*
 340  * Glue for drivers of sa11x0 compatible integrated logics.
 341  */
 342 void *
 343 sa11x0_intr_establish(sa11x0_chipset_tag_t ic, int irq, int type, int level,
 344     int (*ih_fun)(void *), void *ih_arg)
 345 {
 346
 347         return pxa2x0_intr_establish(irq, level, ih_fun, ih_arg);
 348 }