sys/arch/arm/xscale/pxa2x0_rtc.c

   1 /*      $NetBSD: pxa2x0_rtc.c,v 1.2 2009/08/09 06:12:34 kiyohara Exp $  */
   2
   3 /*
   4  * Copyright (c) 2007 NONAKA Kimihiro <nonaka@netbsd.org>
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  16  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  17  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  18  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  19  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  20  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  21  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  22  */
  23
  24 #include <sys/cdefs.h>
  25 __KERNEL_RCSID(0, "$NetBSD: pxa2x0_rtc.c,v 1.2 2009/08/09 06:12:34 kiyohara Exp $");
  26
  27 #include <sys/param.h>
  28 #include <sys/systm.h>
  29 #include <sys/device.h>
  30 #include <sys/kernel.h>
  31
  32 #include <dev/clock_subr.h>
  33
  34 #include <machine/bus.h>
  35
  36 #include <arm/xscale/pxa2x0cpu.h>
  37 #include <arm/xscale/pxa2x0reg.h>
  38 #include <arm/xscale/pxa2x0var.h>
  39
  40 #ifdef PXARTC_DEBUG
  41 #define DPRINTF(s)      printf s
  42 #else
  43 #define DPRINTF(s)
  44 #endif
  45
  46 struct pxartc_softc {
  47         struct device           sc_dev;
  48         bus_space_tag_t         sc_iot;
  49         bus_space_handle_t      sc_ioh;
  50
  51         struct todr_chip_handle sc_todr;
  52
  53         int                     sc_flags;
  54 #define FLAG_WRISTWATCH (1 << 0)
  55 };
  56
  57 static int  pxartc_match(struct device *, struct cfdata *, void *);
  58 static void pxartc_attach(struct device *, struct device *, void *);
  59
  60 CFATTACH_DECL(pxartc, sizeof(struct pxartc_softc),
  61     pxartc_match, pxartc_attach, NULL, NULL);
  62
  63 /* todr(9) interface */
  64 static int pxartc_todr_gettime(todr_chip_handle_t, struct timeval *);
  65 static int pxartc_todr_settime(todr_chip_handle_t, struct timeval *);
  66
  67 static int pxartc_wristwatch_read(struct pxartc_softc *,struct clock_ymdhms *);
  68 static int pxartc_wristwatch_write(struct pxartc_softc *,struct clock_ymdhms *);
  69
  70 static int
  71 pxartc_match(struct device *parent, struct cfdata *cf, void *aux)
  72 {
  73         struct pxaip_attach_args *pxa = aux;
  74
  75         if (strcmp(pxa->pxa_name, cf->cf_name) != 0)
  76                 return 0;
  77
  78         pxa->pxa_size = CPU_IS_PXA270 ? PXA270_RTC_SIZE : PXA250_RTC_SIZE;
  79         return 1;
  80 }
  81
  82 static void
  83 pxartc_attach(struct device *parent, struct device *self, void *aux)
  84 {
  85         struct pxartc_softc *sc = (struct pxartc_softc *)self;
  86         struct pxaip_attach_args *pxa = aux;
  87
  88         sc->sc_iot = pxa->pxa_iot;
  89
  90         aprint_normal(": PXA2x0 Real-time Clock\n");
  91
  92         if (bus_space_map(sc->sc_iot, pxa->pxa_addr, pxa->pxa_size, 0,
  93             &sc->sc_ioh)) {
  94                 aprint_error("%s: couldn't map registers\n",
  95                     sc->sc_dev.dv_xname);
  96                 return;
  97         }
  98
  99         if (pxa->pxa_size == PXA270_RTC_SIZE) {
 100                 aprint_normal("%s: using wristwatch register\n",
 101                     sc->sc_dev.dv_xname);
 102                 sc->sc_flags |= FLAG_WRISTWATCH;
 103         }
 104
 105         sc->sc_todr.cookie = sc;
 106         sc->sc_todr.todr_gettime = pxartc_todr_gettime;
 107         sc->sc_todr.todr_settime = pxartc_todr_settime;
 108         sc->sc_todr.todr_setwen = NULL;
 109
 110         todr_attach(&sc->sc_todr);
 111 }
 112
 113 static int
 114 pxartc_todr_gettime(todr_chip_handle_t ch, struct timeval *tv)
 115 {
 116         struct pxartc_softc *sc = ch->cookie;
 117         struct clock_ymdhms dt;
 118
 119         if ((sc->sc_flags & FLAG_WRISTWATCH) == 0) {
 120                 tv->tv_sec = bus_space_read_4(sc->sc_iot, sc->sc_ioh, RTC_RCNR);
 121                 tv->tv_usec = 0;
 122                 DPRINTF(("%s: RCNR = %08lx\n", sc->sc_dev.dv_xname,tv->tv_sec));
 123 #ifdef PXARTC_DEBUG
 124                 clock_secs_to_ymdhms(tv->tv_sec, &dt);
 125                 DPRINTF(("%s: %02d/%02d/%02d %02d:%02d:%02d\n",
 126                     sc->sc_dev.dv_xname,
 127                     dt.dt_year, dt.dt_mon, dt.dt_day,
 128                     dt.dt_hour, dt.dt_min, dt.dt_sec));
 129 #endif
 130                 return 0;
 131         }
 132
 133         memset(&dt, 0, sizeof(dt));
 134
 135         if (pxartc_wristwatch_read(sc, &dt) == 0)
 136                 return -1;
 137
 138         tv->tv_sec = clock_ymdhms_to_secs(&dt);
 139         tv->tv_usec = 0;
 140         return 0;
 141 }
 142
 143 static int
 144 pxartc_todr_settime(todr_chip_handle_t ch, struct timeval *tv)
 145 {
 146         struct pxartc_softc *sc = ch->cookie;
 147         struct clock_ymdhms dt;
 148
 149         if ((sc->sc_flags & FLAG_WRISTWATCH) == 0) {
 150 #ifdef PXARTC_DEBUG
 151                 DPRINTF(("%s: RCNR = %08lx\n", sc->sc_dev.dv_xname,tv->tv_sec));
 152                 clock_secs_to_ymdhms(tv->tv_sec, &dt);
 153                 DPRINTF(("%s: %02d/%02d/%02d %02d:%02d:%02d\n",
 154                     sc->sc_dev.dv_xname,
 155                     dt.dt_year, dt.dt_mon, dt.dt_day,
 156                     dt.dt_hour, dt.dt_min, dt.dt_sec));
 157 #endif
 158                 bus_space_write_4(sc->sc_iot, sc->sc_ioh, RTC_RCNR, tv->tv_sec);
 159 #ifdef PXARTC_DEBUG
 160                 {
 161                 uint32_t cntr;
 162                 delay(1);
 163                 cntr = bus_space_read_4(sc->sc_iot, sc->sc_ioh, RTC_RCNR);
 164                 DPRINTF(("%s: new RCNR = %08x\n", sc->sc_dev.dv_xname, cntr));
 165                 clock_secs_to_ymdhms(cntr, &dt);
 166                 DPRINTF(("%s: %02d/%02d/%02d %02d:%02d:%02d\n",
 167                     sc->sc_dev.dv_xname,
 168                     dt.dt_year, dt.dt_mon, dt.dt_day,
 169                     dt.dt_hour, dt.dt_min, dt.dt_sec));
 170                 }
 171 #endif
 172                 return 0;
 173         }
 174
 175         clock_secs_to_ymdhms(tv->tv_sec, &dt);
 176
 177         if (pxartc_wristwatch_write(sc, &dt) == 0)
 178                 return -1;
 179         return 0;
 180 }
 181
 182 static int
 183 pxartc_wristwatch_read(struct pxartc_softc *sc, struct clock_ymdhms *dt)
 184 {
 185         uint32_t dayr, yearr;
 186         int s;
 187
 188         DPRINTF(("%s: pxartc_wristwatch_read()\n", sc->sc_dev.dv_xname));
 189
 190         s = splhigh();
 191         dayr = bus_space_read_4(sc->sc_iot, sc->sc_ioh, RTC_RDCR);
 192         yearr = bus_space_read_4(sc->sc_iot, sc->sc_ioh, RTC_RYCR);
 193         splx(s);
 194
 195         DPRINTF(("%s: RDCR = %08x, RYCR = %08x\n", sc->sc_dev.dv_xname,
 196             dayr, yearr));
 197
 198         dt->dt_sec = (dayr >> RDCR_SECOND_SHIFT) & RDCR_SECOND_MASK;
 199         dt->dt_min = (dayr >> RDCR_MINUTE_SHIFT) & RDCR_MINUTE_MASK;
 200         dt->dt_hour = (dayr >> RDCR_HOUR_SHIFT) & RDCR_HOUR_MASK;
 201         dt->dt_day = (yearr >> RYCR_DOM_SHIFT) & RYCR_DOM_MASK;
 202         dt->dt_mon = (yearr >> RYCR_MONTH_SHIFT) & RYCR_MONTH_MASK;
 203         dt->dt_year = (yearr >> RYCR_YEAR_SHIFT) & RYCR_YEAR_MASK;
 204
 205         DPRINTF(("%s: %02d/%02d/%02d %02d:%02d:%02d\n", sc->sc_dev.dv_xname,
 206             dt->dt_year, dt->dt_mon, dt->dt_day,
 207             dt->dt_hour, dt->dt_min, dt->dt_sec));
 208
 209         return 1;
 210 }
 211
 212 static int
 213 pxartc_wristwatch_write(struct pxartc_softc *sc, struct clock_ymdhms *dt)
 214 {
 215         uint32_t dayr, yearr;
 216         uint32_t wom;   /* week of month: 1=first week of month */
 217         int s;
 218
 219         DPRINTF(("%s: pxartc_wristwatch_write()\n", sc->sc_dev.dv_xname));
 220
 221         DPRINTF(("%s: %02d/%02d/%02d %02d:%02d:%02d\n", sc->sc_dev.dv_xname,
 222             dt->dt_year, dt->dt_mon, dt->dt_day,
 223             dt->dt_hour, dt->dt_min, dt->dt_sec));
 224
 225         dayr = (dt->dt_sec & RDCR_SECOND_MASK) << RDCR_SECOND_SHIFT;
 226         dayr |= (dt->dt_min & RDCR_MINUTE_MASK) << RDCR_MINUTE_SHIFT;
 227         dayr |= (dt->dt_hour & RDCR_HOUR_MASK) << RDCR_HOUR_SHIFT;
 228         dayr |= ((dt->dt_wday + 1) & RDCR_DOW_MASK) << RDCR_DOW_SHIFT;
 229         wom = ((dt->dt_day - 1 + 6 - dt->dt_wday) / 7) + 1;
 230         dayr |= (wom & RDCR_WOM_MASK) << RDCR_WOM_SHIFT;
 231         yearr = (dt->dt_day & RYCR_DOM_MASK) << RYCR_DOM_SHIFT;
 232         yearr |= (dt->dt_mon & RYCR_MONTH_MASK) << RYCR_MONTH_SHIFT;
 233         yearr |= (dt->dt_year & RYCR_YEAR_MASK) << RYCR_YEAR_SHIFT;
 234
 235         DPRINTF(("%s: RDCR = %08x, RYCR = %08x\n", sc->sc_dev.dv_xname,
 236             dayr, yearr));
 237
 238         /*
 239          * We must write RYCR register before write RDCR register.
 240          *
 241          * See PXA270 Processor Family Developer's Manual p.946
 242          *   21.4.2.3.1 Writing RDCR and RYCR Counter Registers with Valid Data.
 243          */
 244         s = splhigh();
 245         bus_space_write_4(sc->sc_iot, sc->sc_ioh, RTC_RYCR, yearr);
 246         bus_space_write_4(sc->sc_iot, sc->sc_ioh, RTC_RDCR, dayr);
 247         splx(s);
 248
 249 #ifdef PXARTC_DEBUG
 250         {
 251                 struct clock_ymdhms dummy;
 252                 pxartc_wristwatch_read(sc, &dummy);
 253         }
 254 #endif
 255
 256         return 1;
 257 }