sys/arch/evbarm/ifpga/ifpga_clock.c

   1 /*      $NetBSD: ifpga_clock.c,v 1.13 2009/03/18 10:22:27 cegger Exp $ */
   2
   3 /*
   4  * Copyright (c) 2001 ARM Ltd
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  * 3. The name of the company may not be used to endorse or promote
  16  *    products derived from this software without specific prior written
  17  *    permission.
  18  *
  19  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  20  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  21  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  22  * IN NO EVENT SHALL THE AUTHORS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
  23  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  24  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  25  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  26  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  27  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  28  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  29  * SUCH DAMAGE.
  30  */
  31
  32 /*
  33  * The IFPGA has three timers.  Timer 0 is clocked by the system bus clock,
  34  * while timers 1 and 2 are clocked at 24MHz.  To keep things simple here,
  35  * we use timers 1 and 2 only.  All three timers are 16-bit counters that
  36  * are programmable in either periodic mode or in one-shot mode.
  37  */
  38
  39 /* Include header files */
  40
  41 #include <sys/cdefs.h>
  42 __KERNEL_RCSID(0, "$NetBSD: ifpga_clock.c,v 1.13 2009/03/18 10:22:27 cegger Exp $");
  43
  44 #include <sys/types.h>
  45 #include <sys/param.h>
  46 #include <sys/systm.h>
  47 #include <sys/kernel.h>
  48 #include <sys/atomic.h>
  49 #include <sys/time.h>
  50 #include <sys/timetc.h>
  51 #include <sys/device.h>
  52
  53 #include <arm/cpufunc.h>
  54 #include <machine/intr.h>
  55
  56 #include <evbarm/ifpga/ifpgavar.h>
  57 #include <evbarm/ifpga/ifpgamem.h>
  58 #include <evbarm/ifpga/ifpgareg.h>
  59
  60 /*
  61  * Statistics clock interval and variance, in usec.  Variance must be a
  62  * power of two.  Since this gives us an even number, not an odd number,
  63  * we discard one case and compensate.  That is, a variance of 1024 would
  64  * give us offsets in [0..1023].  Instead, we take offsets in [1..1023].
  65  * This is symmetric about the point 512, or statvar/2, and thus averages
  66  * to that value (assuming uniform random numbers).
  67  */
  68 static int statvar = 1024 / 4;  /* {stat,prof}clock variance */
  69 static int statmin;             /* statclock interval - variance/2 */
  70 static int profmin;             /* profclock interval - variance/2 */
  71 static int timer2min;           /* current, from above choices */
  72 static int statprev;            /* previous value in stat timer */
  73
  74 #define TIMER_1_CLEAR (IFPGA_TIMER1_BASE + TIMERx_CLR)
  75 #define TIMER_1_LOAD  (IFPGA_TIMER1_BASE + TIMERx_LOAD)
  76 #define TIMER_1_VALUE (IFPGA_TIMER1_BASE + TIMERx_VALUE)
  77 #define TIMER_1_CTRL  (IFPGA_TIMER1_BASE + TIMERx_CTRL)
  78
  79 #define TIMER_2_CLEAR (IFPGA_TIMER2_BASE + TIMERx_CLR)
  80 #define TIMER_2_LOAD  (IFPGA_TIMER2_BASE + TIMERx_LOAD)
  81 #define TIMER_2_VALUE (IFPGA_TIMER2_BASE + TIMERx_VALUE)
  82 #define TIMER_2_CTRL  (IFPGA_TIMER2_BASE + TIMERx_CTRL)
  83
  84 #define COUNTS_PER_SEC (IFPGA_TIMER1_FREQ / 16)
  85
  86 static u_int    ifpga_get_timecount(struct timecounter *);
  87
  88 static struct timecounter ifpga_timecounter = {
  89         ifpga_get_timecount,    /* get_timecount */
  90         0,                      /* no poll_pps */
  91         0xffffffff,             /* counter_mask */
  92         COUNTS_PER_SEC,         /* frequency */
  93         "ifpga",                /* name */
  94         100,                    /* quality */
  95         NULL,                   /* prev */
  96         NULL,                   /* next */
  97 };
  98
  99 static volatile uint32_t ifpga_base;
 100
 101 extern struct ifpga_softc *ifpga_sc;
 102 extern device_t ifpga_dev;
 103
 104 static int clock_started = 0;
 105
 106 static int load_timer(int, int);
 107
 108 static inline u_int
 109 getclock(void)
 110 {
 111         return bus_space_read_4(ifpga_sc->sc_iot, ifpga_sc->sc_tmr_ioh,
 112             TIMER_1_VALUE);
 113 }
 114
 115 static inline u_int
 116 getstatclock(void)
 117 {
 118         return bus_space_read_4(ifpga_sc->sc_iot, ifpga_sc->sc_tmr_ioh,
 119             TIMER_2_VALUE);
 120 }
 121
 122 /*
 123  * int clockhandler(struct clockframe *frame)
 124  *
 125  * Function called by timer 1 interrupts.
 126  * This just clears the interrupt condition and calls hardclock().
 127  */
 128
 129 static int
 130 clockhandler(void *fr)
 131 {
 132         struct clockframe *frame = (struct clockframe *)fr;
 133
 134         bus_space_write_4(ifpga_sc->sc_iot, ifpga_sc->sc_tmr_ioh,
 135             TIMER_1_CLEAR, 0);
 136
 137         atomic_add_32(&ifpga_base, ifpga_sc->sc_clock_count);
 138
 139         hardclock(frame);
 140         return 0;       /* Pass the interrupt on down the chain */
 141 }
 142
 143
 144 /*
 145  * int statclockhandler(struct clockframe *frame)
 146  *
 147  * Function called by timer 2 interrupts.
 148  * Add some random jitter to the clock, and then call statclock().
 149  */
 150
 151 static int
 152 statclockhandler(void *fr)
 153 {
 154         struct clockframe *frame = (struct clockframe *) fr;
 155         int newint, r, var;
 156
 157         var = statvar;
 158         do {
 159                 r = random() & (var - 1);
 160         } while (r == 0);
 161         newint = timer2min + r;
 162
 163         if (newint & ~0x0000ffff)
 164                 panic("statclockhandler: statclock variance too large");
 165
 166         /*
 167          * The timer was automatically reloaded with the previous latch
 168          * value at the time of the interrupts.  Compensate now for the
 169          * amount of time that has run off since then, plus one tick
 170          * roundoff.  This should keep us closer to the mean.
 171          */
 172
 173         r = (statprev - getstatclock() + 1);
 174         if (r < newint) {
 175                 newint -= r;
 176                 r = 0;
 177         }
 178         else
 179                 printf("statclockhandler: Statclock overrun\n");
 180
 181         statprev = load_timer(IFPGA_TIMER2_BASE, newint);
 182         statclock(frame);
 183         if (r)
 184                 /*
 185                  * We've completely overrun the previous interval,
 186                  * make sure we report the correct number of ticks.
 187                  */
 188                 statclock(frame);
 189
 190         return 0;       /* Pass the interrupt on down the chain */
 191 }
 192
 193 static int
 194 load_timer(int base, int intvl)
 195 {
 196         int control;
 197
 198         if (intvl & ~0x0000ffff)
 199                 panic("clock: Invalid interval");
 200
 201         control = (TIMERx_CTRL_ENABLE | TIMERx_CTRL_MODE_PERIODIC |
 202             TIMERx_CTRL_PRESCALE_DIV16);
 203
 204         bus_space_write_4(ifpga_sc->sc_iot, ifpga_sc->sc_tmr_ioh,
 205             base + TIMERx_LOAD, intvl);
 206         bus_space_write_4(ifpga_sc->sc_iot, ifpga_sc->sc_tmr_ioh,
 207             base + TIMERx_CTRL, control);
 208         bus_space_write_4(ifpga_sc->sc_iot, ifpga_sc->sc_tmr_ioh,
 209             base + TIMERx_CLR, 0);
 210         return intvl;
 211 }
 212
 213 /*
 214  * void setstatclockrate(int hz)
 215  *
 216  * We assume that hz is either stathz or profhz, and that neither will
 217  * change after being set by cpu_initclocks().  We could recalculate the
 218  * intervals here, but that would be a pain.
 219  */
 220
 221 void
 222 setstatclockrate(int new_hz)
 223 {
 224         if (new_hz == stathz)
 225                 timer2min = statmin;
 226         else
 227                 timer2min = profmin;
 228 }
 229
 230 /*
 231  * void cpu_initclocks(void)
 232  *
 233  * Initialise the clocks.
 234  */
 235
 236 void
 237 cpu_initclocks(void)
 238 {
 239         int intvl;
 240         int statint;
 241         int profint;
 242         int minint;
 243
 244         if (hz < 50 || COUNTS_PER_SEC % hz) {
 245                 printf("cannot get %d Hz clock; using 100 Hz\n", hz);
 246                 hz = 100;
 247                 tick = 1000000 / hz;
 248         }
 249
 250         if (stathz == 0)
 251                 stathz = hz;
 252         else if (stathz < 50 || COUNTS_PER_SEC % stathz) {
 253                 printf("cannot get %d Hz statclock; using 100 Hz\n", stathz);
 254                 stathz = 100;
 255         }
 256
 257         if (profhz == 0)
 258                 profhz = stathz * 5;
 259         else if (profhz < stathz || COUNTS_PER_SEC % profhz) {
 260                 printf("cannot get %d Hz profclock; using %d Hz\n", profhz,
 261                     stathz);
 262                 profhz = stathz;
 263         }
 264
 265         intvl = COUNTS_PER_SEC / hz;
 266         statint = COUNTS_PER_SEC / stathz;
 267         profint = COUNTS_PER_SEC / profhz;
 268         minint = statint / 2 + 100;
 269         while (statvar > minint)
 270                 statvar >>= 1;
 271
 272         /* Adjust interval counts, per note above.  */
 273         intvl--;
 274         statint--;
 275         profint--;
 276
 277         /* Calculate the base reload values.  */
 278         statmin = statint - (statvar >> 1);
 279         profmin = profint - (statvar >> 1);
 280         timer2min = statmin;
 281         statprev = statint;
 282
 283         /* Report the clock frequencies */
 284         printf("clock: hz=%d stathz = %d profhz = %d\n", hz, stathz, profhz);
 285
 286         /* Setup timer 1 and claim interrupt */
 287         ifpga_sc->sc_clockintr = ifpga_intr_establish(IFPGA_TIMER1_IRQ,
 288             IPL_CLOCK, clockhandler, 0);
 289         if (ifpga_sc->sc_clockintr == NULL)
 290                 panic("%s: Cannot install timer 1 interrupt handler",
 291                     device_xname(ifpga_dev));
 292
 293         ifpga_sc->sc_clock_count
 294             = load_timer(IFPGA_TIMER1_BASE, intvl);
 295
 296         /*
 297          * Use ticks per 256us for accuracy since ticks per us is often
 298          * fractional e.g. @ 66MHz
 299          */
 300         ifpga_sc->sc_clock_ticks_per_256us =
 301             ((((ifpga_sc->sc_clock_count * hz) / 1000) * 256) / 1000);
 302
 303         clock_started = 1;
 304
 305         /* Set up timer 2 as statclk/profclk. */
 306         ifpga_sc->sc_statclockintr = ifpga_intr_establish(IFPGA_TIMER2_IRQ,
 307             IPL_HIGH, statclockhandler, 0);
 308         if (ifpga_sc->sc_statclockintr == NULL)
 309                 panic("%s: Cannot install timer 2 interrupt handler",
 310                     device_xname(ifpga_dev));
 311         load_timer(IFPGA_TIMER2_BASE, statint);
 312
 313         tc_init(&ifpga_timecounter);
 314 }
 315
 316 static u_int
 317 ifpga_get_timecount(struct timecounter *tc)
 318 {
 319         u_int base, counter;
 320
 321         do {
 322                 base = ifpga_base;
 323                 counter = getclock();
 324         } while (base != ifpga_base);
 325
 326         return base - counter;
 327 }
 328
 329 /*
 330  * Estimated loop for n microseconds
 331  */
 332
 333 /* Need to re-write this to use the timers */
 334
 335 /* One day soon I will actually do this */
 336
 337 int delaycount = 50;
 338
 339 void
 340 delay(u_int n)
 341 {
 342         if (clock_started) {
 343                 u_int starttime;
 344                 u_int curtime;
 345                 u_int delta = 0;
 346                 u_int count_max = ifpga_sc->sc_clock_count;
 347
 348                 starttime = getclock();
 349
 350                 n *= IFPGA_TIMER1_FREQ / 1000000;
 351
 352                 do {
 353                         n -= delta;
 354                         curtime = getclock();
 355                         delta = curtime - starttime;
 356                         if (curtime < starttime)
 357                                 delta += count_max;
 358                         starttime = curtime;
 359                 } while (n > delta);
 360         } else {
 361                 volatile u_int i;
 362
 363                 if (n == 0) return;
 364                 while (n-- > 0) {
 365                         /* XXX - Seriously gross hack */
 366                         if (cputype == CPU_ID_SA110)
 367                                 for (i = delaycount; --i;)
 368                                         ;
 369                         else
 370                                 for (i = 8; --i;)
 371                                         ;
 372                 }
 373         }
 374 }