sys/arch/evbarm/iq80310/iq80310_timer.c

   1 /*      $NetBSD: iq80310_timer.c,v 1.20 2007/02/19 02:08:12 briggs Exp $        */
   2
   3 /*
   4  * Copyright (c) 2001, 2002 Wasabi Systems, Inc.
   5  * All rights reserved.
   6  *
   7  * Written by Jason R. Thorpe for Wasabi Systems, Inc.
   8  *
   9  * Redistribution and use in source and binary forms, with or without
  10  * modification, are permitted provided that the following conditions
  11  * are met:
  12  * 1. Redistributions of source code must retain the above copyright
  13  *    notice, this list of conditions and the following disclaimer.
  14  * 2. Redistributions in binary form must reproduce the above copyright
  15  *    notice, this list of conditions and the following disclaimer in the
  16  *    documentation and/or other materials provided with the distribution.
  17  * 3. All advertising materials mentioning features or use of this software
  18  *    must display the following acknowledgement:
  19  *      This product includes software developed for the NetBSD Project by
  20  *      Wasabi Systems, Inc.
  21  * 4. The name of Wasabi Systems, Inc. may not be used to endorse
  22  *    or promote products derived from this software without specific prior
  23  *    written permission.
  24  *
  25  * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
  26  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  27  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  28  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
  29  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  30  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  31  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  32  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  33  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  34  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  35  * POSSIBILITY OF SUCH DAMAGE.
  36  */
  37
  38 /*
  39  * Timer/clock support for the Intel IQ80310.
  40  *
  41  * The IQ80310 has a 22-bit reloadable timer implemented in the CPLD.
  42  * We use it to provide a hardclock interrupt.  There is no RTC on
  43  * the IQ80310.
  44  *
  45  * The timer uses the SPCI clock.  The timer uses the 33MHz clock by
  46  * reading the SPCI_66EN signal and dividing the clock if necessary.
  47  */
  48
  49 #include <sys/cdefs.h>
  50 __KERNEL_RCSID(0, "$NetBSD: iq80310_timer.c,v 1.20 2007/02/19 02:08:12 briggs Exp $");
  51
  52 #include <sys/param.h>
  53 #include <sys/systm.h>
  54 #include <sys/kernel.h>
  55 #include <sys/atomic.h>
  56 #include <sys/time.h>
  57 #include <sys/timetc.h>
  58
  59 #include <dev/clock_subr.h>
  60
  61 #include <machine/bus.h>
  62 #include <arm/cpufunc.h>
  63
  64 #include <evbarm/iq80310/iq80310reg.h>
  65 #include <evbarm/iq80310/iq80310var.h>
  66 #include <evbarm/iq80310/obiovar.h>
  67
  68 /*
  69  * Some IQ80310-based designs have fewer bits in the timer counter.
  70  * Deal with them here.
  71  */
  72 #if defined(IOP310_TEAMASA_NPWR)
  73 #define COUNTER_MASK            0x0007ffff
  74 #else /* Default to stock IQ80310 */
  75 #define COUNTER_MASK            0x003fffff
  76 #endif /* list of IQ80310-based designs */
  77
  78 #define COUNTS_PER_SEC          33000000        /* 33MHz */
  79 #define COUNTS_PER_USEC         (COUNTS_PER_SEC / 1000000)
  80
  81 static void *clock_ih;
  82
  83 static uint32_t counts_per_hz;
  84
  85 static u_int    iq80310_get_timecount(struct timecounter *);
  86
  87 static struct timecounter iq80310_timecounter = {
  88         iq80310_get_timecount,  /* get_timecount */
  89         0,                      /* no poll_pps */
  90         0xffffffff,             /* counter_mask */
  91         COUNTS_PER_SEC,         /* frequency */
  92         "iq80310",              /* name */
  93         100,                    /* quality */
  94         NULL,                   /* prev */
  95         NULL,                   /* next */
  96 };
  97
  98 static volatile uint32_t iq80310_base;
  99
 100 int     clockhandler(void *);
 101
 102 static inline void
 103 timer_enable(uint8_t bit)
 104 {
 105
 106         CPLD_WRITE(IQ80310_TIMER_ENABLE,
 107             CPLD_READ(IQ80310_TIMER_ENABLE) | bit);
 108 }
 109
 110 static inline void
 111 timer_disable(uint8_t bit)
 112 {
 113
 114         CPLD_WRITE(IQ80310_TIMER_ENABLE,
 115             CPLD_READ(IQ80310_TIMER_ENABLE) & ~bit);
 116 }
 117
 118 static inline uint32_t
 119 timer_read(void)
 120 {
 121         uint32_t rv;
 122         uint8_t la0, la1, la2, la3;
 123
 124         /*
 125          * First read latches count.
 126          *
 127          * From RedBoot: harware bug that causes invalid counts to be
 128          * latched.  The loop appears to work around the problem.
 129          */
 130         do {
 131                 la0 = CPLD_READ(IQ80310_TIMER_LA0);
 132         } while (la0 == 0);
 133         la1 = CPLD_READ(IQ80310_TIMER_LA1);
 134         la2 = CPLD_READ(IQ80310_TIMER_LA2);
 135         la3 = CPLD_READ(IQ80310_TIMER_LA3);
 136
 137         rv  =  ((la0 & 0x40) >> 1) | (la0 & 0x1f);
 138         rv |= (((la1 & 0x40) >> 1) | (la1 & 0x1f)) << 6;
 139         rv |= (((la2 & 0x40) >> 1) | (la2 & 0x1f)) << 12;
 140         rv |= (la3 & 0x0f) << 18;
 141
 142         return (rv);
 143 }
 144
 145 static inline void
 146 timer_write(uint32_t x)
 147 {
 148
 149         KASSERT((x & COUNTER_MASK) == x);
 150
 151         CPLD_WRITE(IQ80310_TIMER_LA0, x & 0xff);
 152         CPLD_WRITE(IQ80310_TIMER_LA1, (x >> 8) & 0xff);
 153         CPLD_WRITE(IQ80310_TIMER_LA2, (x >> 16) & 0x3f);
 154 }
 155
 156 /*
 157  * iq80310_calibrate_delay:
 158  *
 159  *      Calibrate the delay loop.
 160  */
 161 void
 162 iq80310_calibrate_delay(void)
 163 {
 164
 165         /*
 166          * We'll use the CPLD timer for delay(), as well.  We go
 167          * ahead and start it up now, just don't enable interrupts
 168          * until cpu_initclocks().
 169          *
 170          * Just use hz=100 for now -- we'll adjust it, if necessary,
 171          * in cpu_initclocks().
 172          */
 173         counts_per_hz = COUNTS_PER_SEC / 100;
 174
 175         timer_disable(TIMER_ENABLE_INTEN);
 176         timer_disable(TIMER_ENABLE_EN);
 177
 178         timer_write(counts_per_hz);
 179
 180         timer_enable(TIMER_ENABLE_EN);
 181 }
 182
 183 /*
 184  * cpu_initclocks:
 185  *
 186  *      Initialize the clock and get them going.
 187  */
 188 void
 189 cpu_initclocks(void)
 190 {
 191         u_int oldirqstate;
 192
 193         if (hz < 50 || COUNTS_PER_SEC % hz) {
 194                 printf("Cannot get %d Hz clock; using 100 Hz\n", hz);
 195                 hz = 100;
 196         }
 197
 198         /*
 199          * We only have one timer available; stathz and profhz are
 200          * always left as 0 (the upper-layer clock code deals with
 201          * this situation).
 202          */
 203         if (stathz != 0)
 204                 printf("Cannot get %d Hz statclock\n", stathz);
 205         stathz = 0;
 206
 207         if (profhz != 0)
 208                 printf("Cannot get %d Hz profclock\n", profhz);
 209         profhz = 0;
 210
 211         /* Report the clock frequency. */
 212         printf("clock: hz=%d stathz=%d profhz=%d\n", hz, stathz, profhz);
 213
 214         /* Hook up the clock interrupt handler. */
 215         clock_ih = iq80310_intr_establish(XINT3_IRQ(XINT3_TIMER), IPL_CLOCK,
 216             clockhandler, NULL);
 217         if (clock_ih == NULL)
 218                 panic("cpu_initclocks: unable to register timer interrupt");
 219
 220         /* Set up the new clock parameters. */
 221         oldirqstate = disable_interrupts(I32_bit);
 222
 223         timer_disable(TIMER_ENABLE_EN);
 224
 225         counts_per_hz = COUNTS_PER_SEC / hz;
 226         timer_write(counts_per_hz);
 227
 228         timer_enable(TIMER_ENABLE_INTEN);
 229         timer_enable(TIMER_ENABLE_EN);
 230
 231         restore_interrupts(oldirqstate);
 232
 233         tc_init(&iq80310_timecounter);
 234 }
 235
 236 /*
 237  * setstatclockrate:
 238  *
 239  *      Set the rate of the statistics clock.
 240  *
 241  *      We assume that hz is either stathz or profhz, and that neither
 242  *      will change after being set by cpu_initclocks().  We could
 243  *      recalculate the intervals here, but that would be a pain.
 244  */
 245 void
 246 setstatclockrate(int newhz)
 247 {
 248
 249         /*
 250          * Nothing to do, here; we can't change the statclock
 251          * rate on the IQ80310.
 252          */
 253 }
 254
 255 static u_int
 256 iq80310_get_timecount(struct timecounter *tc)
 257 {
 258         u_int oldirqstate, base, counter;
 259
 260         oldirqstate = disable_interrupts(I32_bit);
 261         base = iq80310_base;
 262         counter = timer_read();
 263         restore_interrupts(oldirqstate);
 264
 265         return base + counter;
 266 }
 267
 268 /*
 269  * delay:
 270  *
 271  *      Delay for at least N microseconds.
 272  */
 273 void
 274 delay(u_int n)
 275 {
 276         uint32_t cur, last, delta, usecs;
 277
 278         /*
 279          * This works by polling the timer and counting the
 280          * number of microseconds that go by.
 281          */
 282         last = timer_read();
 283         delta = usecs = 0;
 284
 285         while (n > usecs) {
 286                 cur = timer_read();
 287
 288                 /* Check to see if the timer has wrapped around. */
 289                 if (cur < last)
 290                         delta += ((counts_per_hz - last) + cur);
 291                 else
 292                         delta += (cur - last);
 293
 294                 last = cur;
 295
 296                 if (delta >= COUNTS_PER_USEC) {
 297                         usecs += delta / COUNTS_PER_USEC;
 298                         delta %= COUNTS_PER_USEC;
 299                 }
 300         }
 301 }
 302
 303 /*
 304  * clockhandler:
 305  *
 306  *      Handle the hardclock interrupt.
 307  */
 308 int
 309 clockhandler(void *arg)
 310 {
 311         struct clockframe *frame = arg;
 312
 313         timer_disable(TIMER_ENABLE_INTEN);
 314         timer_enable(TIMER_ENABLE_INTEN);
 315
 316         atomic_add_32(&iq80310_base, counts_per_hz);
 317
 318         hardclock(frame);
 319
 320         /*
 321          * Don't run the snake on IOP310-based systems that
 322          * don't have the 7-segment display.
 323          */
 324 #if !defined(IOP310_TEAMASA_NPWR)
 325         {
 326                 static int snakefreq;
 327
 328                 if ((snakefreq++ & 15) == 0)
 329                         iq80310_7seg_snake();
 330         }
 331 #endif
 332
 333         return (1);
 334 }