sys/arch/evbarm/ixm1200/nappi_nppb.c

   1 /*      $NetBSD: nappi_nppb.c,v 1.6 2003/03/25 06:53:16 igy Exp $ */
   2 /*
   3  * Copyright (c) 2002, 2003
   4  *      Ichiro FUKUHARA <ichiro@ichiro.org>.
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR
  17  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  18  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  19  * IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR
  20  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  26  * SUCH DAMAGE.
  27  */
  28
  29 #include <sys/cdefs.h>
  30 __KERNEL_RCSID(0, "$NetBSD: nappi_nppb.c,v 1.6 2003/03/25 06:53:16 igy Exp $");
  31
  32 #include "pci.h"
  33 #include "opt_pci.h"
  34
  35 #include <sys/types.h>
  36 #include <sys/param.h>
  37 #include <sys/systm.h>
  38 #include <sys/device.h>
  39 #include <sys/extent.h>
  40 #include <sys/malloc.h>
  41
  42 #include <machine/bus.h>
  43
  44 #include <dev/pci/pcivar.h>
  45 #include <dev/pci/pcireg.h>
  46 #include <dev/pci/pcidevs.h>
  47 #include <dev/pci/pciconf.h>
  48
  49 static int      nppbmatch(struct device *, struct cfdata *, void *);
  50 static void     nppbattach(struct device *, struct device *, void *);
  51
  52 int     nppb_intr(void *); /* XXX into i21555var.h */
  53
  54 CFATTACH_DECL(nppb, sizeof(struct device),
  55     nppbmatch, nppbattach, NULL, NULL);
  56
  57 #define NPPB_MMBA       0x10
  58 #define NPPB_IOBA       0x14
  59
  60 #define CSR_READ_1(sc, reg)     \
  61         bus_space_read_1(sc->sc_st, sc->sc_sh, reg)
  62 #define CSR_READ_2(sc, reg)     \
  63         bus_space_read_2(sc->sc_st, sc->sc_sh, reg)
  64 #define CSR_READ_4(sc, reg)     \
  65         bus_space_read_4(sc->sc_st, sc->sc_sh, reg)
  66
  67 #define CSR_WRITE_1(sc, reg, val)       \
  68         bus_space_write_1(sc->sc_st, sc->sc_sh, reg, val)
  69 #define CSR_WRITE_2(sc, reg, val)       \
  70         bus_space_write_2(sc->sc_st, sc->sc_sh, reg, val)
  71 #define CSR_WRITE_4(sc, reg, val)       \
  72         bus_space_write_4(sc->sc_st, sc->sc_sh, reg, val)
  73
  74 struct nppb_softc {  /* XXX into i21555var.h */
  75         struct device sc_dev;           /* generic device information */
  76         bus_space_tag_t sc_st;          /* bus space tag */
  77         bus_space_handle_t sc_sh;       /* bus space handle */
  78
  79         void *sc_ih;                    /* interrupt handler cookie */
  80 };
  81
  82 struct nppb_pci_softc {
  83         struct nppb_softc psc_nppb;
  84
  85         pci_chipset_tag_t psc_pc;       /* pci chipset tag */
  86         pcitag_t psc_tag;               /* pci register tag */
  87 };
  88
  89 static int
  90 nppbmatch(struct device *parent, struct cfdata *cf, void *aux)
  91 {
  92         struct pci_attach_args *pa = aux;
  93         u_int32_t class, id;
  94
  95         class = pa->pa_class;
  96         id = pa->pa_id;
  97
  98         if (PCI_CLASS(class) == PCI_CLASS_BRIDGE &&
  99             PCI_SUBCLASS(class) == PCI_SUBCLASS_BRIDGE_MISC) {
 100                 switch (PCI_VENDOR(id)) {
 101                 case PCI_VENDOR_INTEL:
 102                         switch (PCI_PRODUCT(id)) {
 103                         case PCI_PRODUCT_INTEL_21555:
 104                             return(1);
 105                         }
 106                         break;
 107                 }
 108         }
 109         return(0);
 110 }
 111
 112 static void
 113 nppbattach(struct device *parent, struct device *self, void *aux)
 114 {
 115         struct nppb_pci_softc *psc = (struct nppb_pci_softc *)self;
 116         struct nppb_softc *sc = (struct nppb_softc *)self;
 117         struct pci_attach_args *pa = aux;
 118         pci_chipset_tag_t pc = pa->pa_pc;
 119         pci_intr_handle_t ih;
 120         const char *intrstr = NULL;
 121         char devinfo[256];
 122
 123         bus_space_tag_t iot, memt;
 124         bus_space_handle_t ioh, memh;
 125         int ioh_valid, memh_valid;
 126
 127         psc->psc_pc = pc;
 128         psc->psc_tag = pa->pa_tag;
 129
 130         sprintf(devinfo, "21555 Non-Transparent PCI-PCI Bridge");
 131         aprint_normal(": %s, rev %d\n", devinfo, PCI_REVISION(pa->pa_class));
 132
 133         /* Make sure bus-mastering is enabled. */
 134         pci_conf_write(psc->psc_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG,
 135             pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) |
 136             PCI_COMMAND_MASTER_ENABLE);
 137
 138         /* Chip Reset */
 139         pci_conf_write(psc->psc_pc, pa->pa_tag, 0xD8, 0x03);
 140
 141         /* Map control/status registers */
 142         ioh_valid = (pci_mapreg_map(pa, NPPB_IOBA,
 143                         PCI_MAPREG_TYPE_IO, 0,
 144                         &iot, &ioh, NULL, NULL) == 0);
 145         memh_valid = (pci_mapreg_map(pa, NPPB_MMBA,
 146                         PCI_MAPREG_TYPE_MEM |
 147                         PCI_MAPREG_MEM_TYPE_32BIT,
 148                         0, &memt, &memh, NULL, NULL) == 0);
 149
 150         if (memh_valid) {
 151             sc->sc_st = memt;
 152             sc->sc_sh = memh;
 153         } else if (ioh_valid) {
 154             sc->sc_st = iot;
 155             sc->sc_sh = ioh;
 156         } else {
 157             printf(": unable to map device registers\n");
 158             return;
 159         }
 160
 161         /* Map and establish our interrupt */
 162         if (pci_intr_map(pa, &ih)) {
 163                 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname);
 164                 return;
 165         }
 166         intrstr = pci_intr_string(pc, ih);
 167         sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, nppb_intr, sc);
 168         if (sc->sc_ih == NULL) {
 169                 printf("%s: couldn't establish interrupt",
 170                     sc->sc_dev.dv_xname);
 171                 if (intrstr != NULL)
 172                         printf(" at %s", intrstr);
 173                 printf("\n");
 174                 return;
 175         }
 176         printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr);
 177
 178 }
 179
 180 /* XXX */
 181 int
 182 nppb_intr(void *arg)
 183 {
 184 #if 0
 185         struct nppb_softc *sc = arg;
 186 #endif
 187 #ifdef PCI_DEBUG
 188         printf("nppb_intr assert\n");
 189 #endif
 190         return(0);
 191 }