sys/arch/ews4800mips/include/sbd.h

   1 /*      $NetBSD: sbd.h,v 1.1 2005/12/29 15:20:09 tsutsui Exp $  */
   2
   3 /*-
   4  * Copyright (c) 2004 The NetBSD Foundation, Inc.
   5  * All rights reserved.
   6  *
   7  * This code is derived from software contributed to The NetBSD Foundation
   8  * by UCHIYAMA Yasushi.
   9  *
  10  * Redistribution and use in source and binary forms, with or without
  11  * modification, are permitted provided that the following conditions
  12  * are met:
  13  * 1. Redistributions of source code must retain the above copyright
  14  *    notice, this list of conditions and the following disclaimer.
  15  * 2. Redistributions in binary form must reproduce the above copyright
  16  *    notice, this list of conditions and the following disclaimer in the
  17  *    documentation and/or other materials provided with the distribution.
  18  *
  19  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
  20  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  21  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  22  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  23  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  29  * POSSIBILITY OF SUCH DAMAGE.
  30  */
  31
  32 #ifndef _EWS4800MIPS_SBD_H_
  33 #define _EWS4800MIPS_SBD_H_
  34 /* System board model independ definition */
  35
  36 struct sbdinfo {
  37         uint32_t machine        :16;
  38         uint32_t model          :16;
  39         uint32_t mmu            :1;
  40         uint32_t cache          :1;
  41         uint32_t panel          :2;
  42         uint32_t padding1       :12;
  43         uint32_t fdd            :8;
  44         uint32_t kb             :8;
  45         uint32_t cpu            :4;
  46         uint32_t fpp            :4;
  47         uint32_t fpa            :4;
  48         uint32_t iop            :4;
  49         uint32_t padding2       :16;    /* ----350---- */
  50         uint32_t clock          :32;
  51         char     model_name[20];
  52         uint32_t padding3       :24;
  53         uint32_t ipl            :8;
  54         uint32_t cpu_ex         :32;
  55         uint32_t fpp_ex         :32;    /* ----360---- */
  56         uint32_t padding4       :16;
  57         uint32_t kbms           :4;
  58         uint32_t sio            :4;
  59         uint32_t battery        :8;
  60         uint32_t scsi           :32;
  61 } __attribute__((__packed__));
  62
  63 enum sbd_machine_type {
  64         MACHINE_TR2     = 0x1017,       /* EWS4800/350 */
  65         MACHINE_TR2A    = 0x101f        /* EWS4800/360 */
  66 };
  67
  68 /* Model independent ROM entries */
  69 #define SBD_INFO        ((struct sbdinfo *)0xbfc0fe00)
  70 #define ROM_ADDR        0xbfc00000
  71 #define ROM_SIZE        0x00080000
  72 /* ROM_DK_RW(unit|flag, sector, count, addr) */
  73 #define ROM_DK_RW       ((int (*)(int, uint32_t, uint32_t, void *))0xbfc0ff30)
  74 #define ROM_DK_READ(u, s, c, a)         ROM_DK_RW(u, s, c, a)
  75 #define ROM_DK_WRITE(u, s, c, a)        ROM_DK_RW(u | 0x1000, s, c, a)
  76 /* int ROM_GETC(void) */
  77 #define ROM_GETC        ((int (*)(void))0xbfc0ff50)
  78 /* void ROM_PUTC(xpixel, ypixel, c) */
  79 #define ROM_PUTC        ((void (*)(int, int, int))0xbfc0ff60)
  80 /* ROM_FD_RW(unit | flag, cylinder << 16 | side << 8 | sector, count, addr) */
  81 #define ROM_FD_RW       ((int (*)(int, uint32_t, uint32_t, void *))0xbfc0ff20)
  82 #define ROM_FD_READ(u, s, c, a)         ROM_FD_RW(u, s, c, a)
  83 #define ROM_FD_WRITE(u, s, c, a)        ROM_FD_RW(u | 0x1000, s, c, a)
  84
  85 #define ROM_ETHER_IPL   0xbfc0ff40
  86 #define ROM_CGMT_READ   0xbfc0ff48
  87 #define ROM_PRINTF      0xbfc0ff58
  88 #define ROM_NETIPL      0xbfc0ff68
  89
  90 #define ROM_MONITOR     ((void (*)(void))0xbfc0ff08)
  91 #define ROM_CPUITF      0xbfc0ff00      /* machine check */
  92 #define ROM_SPP         0xbfc0ff70
  93 #define ROM_SPPBP       0xbfc0ff78
  94
  95 #define ROM_FONT_WIDTH          12
  96 #define ROM_FONT_HEIGHT         24
  97
  98 /* NVSRAM */
  99 #define NVSRAM_BOOTDEV_MIN              0
 100 #define NVSRAM_BOOTDEV_FLOPPYDISK       0
 101 #define NVSRAM_BOOTDEV_HARDDISK         2
 102 #define NVSRAM_BOOTDEV_CGMT             4
 103 #define NVSRAM_BOOTDEV_NETWORK          6
 104 #define NVSRAM_BOOTDEV_NETWORK_T_AND_D  8
 105 #define NVSRAM_BOOTDEV_MAX              8
 106
 107 /* RAM */
 108 struct mainfo_type1 {
 109         uint32_t reserved:14,
 110             m8:2, m7:2, m6:2, m5:2, m4:2, m3:2, m2:2, m1:2, m0:2;
 111 };
 112 /* TR2, TR2A */
 113 struct mainfo_type2 {
 114         uint32_t m7:4, m6:4, m5:4, m4:4, m3:4, m2:4, m1:4, m0:4;
 115 };
 116 #define MA0_ADDR                0x00000000
 117 #define __M0_BANK0_ADDR         0x00000000
 118 #define __M0_BANK1_ADDR         0x04000000
 119 #define MA1_ADDR                0x08000000
 120 #define __M1_BANK0_ADDR         0x08000000
 121 #define __M1_BANK1_ADDR         0x0c000000
 122 #define MA2_ADDR                0x10000000
 123 #define __M2_BANK0_ADDR         0x10000000
 124 #define __M2_BANK1_ADDR         0x14000000
 125
 126 #define TR2A_MA3_ADDR           0x20000000
 127 #define TR2_MA3_ADDR            0x38000000
 128
 129 #endif /* !_EWS4800MIPS_SBD_H_ */