sys/arch/hpcarm/dev/ipaq_lcdreg.h

   1 /*      $NetBSD: ipaq_lcdreg.h,v 1.1 2001/07/10 18:09:33 ichiro Exp $ */
   2
   3 /*-
   4  * Copyright (c) 2001 The NetBSD Foundation, Inc.
   5  * All rights reserved.
   6  *
   7  * This code is derived from software contributed to The NetBSD Foundation
   8  * by Ichiro FUKUHARA(ichiro@ichiro.org).
   9  *
  10  * Redistribution and use in source and binary forms, with or without
  11  * modification, are permitted provided that the following conditions
  12  * are met:
  13  * 1. Redistributions of source code must retain the above copyright
  14  *    notice, this list of conditions and the following disclaimer.
  15  * 2. Redistributions in binary form must reproduce the above copyright
  16  *    notice, this list of conditions and the following disclaimer in the
  17  *    documentation and/or other materials provided with the distribution.
  18  *
  19  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
  20  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  21  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  22  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  23  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  29  * POSSIBILITY OF SUCH DAMAGE.
  30  */
  31
  32 /* size of I/O space */
  33 #define SALCD_NPORTS      11
  34
  35 /* LCD framebuffer offset */
  36 #define SALCD_12_16_OFFSET      0x20    /* 12BIT - 16BIT */
  37 #define SALCD_8BIT_OFFSET       0x200   /*  8BIT */
  38
  39 /* LCD Control Register 0 */
  40 #define SALCD_CR0       0
  41 #define CR0_LEN         (1<<0)  /* LCD enable */
  42 #define CR0_CMS         (1<<1)  /* color op enable */
  43 #define CR0_SDS         (1<<2)  /* Single display or Double display */
  44 #define CR0_LDM         (1<<3)  /* LDD status bit ignore(dont intrrupt) */
  45 #define CR0_BAM         (1<<4)  /* Base address update does not
  46                                                 generate an intrrupt */
  47 #define CR0_ERM         (1<<5)  /* Bus error generate an intrrupt */
  48 #define CR0_PAS         (1<<7)  /* Passive / Active and TFT-LCD enable */
  49 #define CR0_BLE         (1<<8)  /* endian select 0=little */
  50 #define CR0_DPD         (1<<9)
  51
  52 /* LCD Control Register 1 */
  53 #define SALCD_CR1       0x20
  54 #define CR1_PPL(pixel)  ((pixel) - 16)          /* PPL ; Pixel per line
  55                                                                  - 16 */
  56 #define CR1_HSW(pixel)  (((pixel) - 1) << 10)   /* HSW ; */
  57 #define CR1_ELW(pixel)  (((pixel) - 1) << 16)   /* ELW ; */
  58 #define CR1_BLW(pixel)  (((pixel) - 1) << 24)   /* BLW ; */
  59
  60 /* LCD Control Register 2 */
  61 #define SALCD_CR2       0x24
  62 #define CR2_LPP(line)   ((line) - 1)            /* LPP ; Lines per panel */
  63 #define CR2_VSW(line)   (((line) -1) << 10)     /* VSW ; */
  64 #define CR2_EFW(line)   ((line) << 16)          /* EFW ; */
  65 #define CR2_BFW(line)   ((line) << 24)          /* BFW ; */
  66
  67 /* LCD Control Register 3 */
  68 #define SALCD_CR3       0x28
  69 #define CR3_PCD(div)    (((div) - 4)/2) /* PCD ; Pixel clock divisor */
  70 #define CR3_ACB(div)    (((div) - 2)/2) /* ACB ; */
  71 #define CR3_API(div)    ((div) << 16)   /* API ; AC Bias */
  72 #define CR3_VSPL        (0 << 20)       /* VSP ; Vsync = Low */
  73 #define CR3_VSPH        (1 << 20)       /* VSP ; Vsync = High */
  74 #define CR3_HSPL        (0 << 21)       /* HSP ; Hsync = Low */
  75 #define CR3_HSPH        (1 << 21)       /* HSP ; Hsync = High */
  76 #define CR3_PCP_RE      (0 << 22)       /* PCP ; Pixel clock Rising-Edge */
  77 #define CR3_PCP_FE      (1 << 22)       /* PCP ; Pixel clock Falling-Edge */
  78 #define CR3_OEPH        (0 << 23)       /* OEP ; Output Enable active High */
  79 #define CR3_OEPL        (0 << 23)       /* OEP ; Output Enable active Low */
  80
  81
  82 /* DMA Channel 1 Base Address Register */
  83 #define SALCD_BA1       0x10
  84
  85 /* DMA Channel 1 Current Address Register */
  86 #define SALCD_CA1       0x14
  87
  88 /* DMA Channel 1 Base Address Register */
  89 #define SALCD_BA2       0x18
  90
  91 /* DMA Channel 1 Current Address Register */
  92 #define SALCD_CA2       0x1C
  93
  94 /* LCD Status Register */
  95 #define SALCD_SR        0x04
  96 #define SR_LDD          (1<<0)
  97 #define SR_BAU          (1<<1)
  98 #define SR_BER          (1<<2)
  99 #define SR_ABC          (1<<3)
 100 #define SR_IOL          (1<<4)
 101 #define SR_IUL          (1<<5)
 102 #define SR_IOU          (1<<6)
 103 #define SR_IUU          (1<<7)
 104 #define SR_OOL          (1<<8)
 105 #define SR_OUL          (1<<9)
 106 #define SR_OOU          (1<<10)
 107 #define SR_OUU          (1<<11)
 108
 109 /* Products Specification */
 110 #define IPAQ_LCCR0      CR0_LEN | CR0_PAS
 111 #define IPAQ_LCCR1      CR1_PPL(320) | CR1_HSW(3) | \
 112                         CR1_ELW(17) | CR1_BLW(12)
 113 #define IPAQ_LCCR2      CR2_LPP(240) | CR2_VSW(3) | \
 114                         CR2_EFW(1) | CR2_BFW(10)
 115 #define IPAQ_LCCR3      CR3_PCD(36) | CR3_ACB(2) | \
 116                         CR3_VSPL | CR3_HSPL | CR3_API(0)
 117
 118 /* end of ipaq_lcdreg.h */