sys/arch/hpcmips/tx/tx39icureg.h

   1 /*      $NetBSD: tx39icureg.h,v 1.4 2001/06/14 11:09:55 uch Exp $ */
   2
   3 /*-
   4  * Copyright (c) 1999 The NetBSD Foundation, Inc.
   5  * All rights reserved.
   6  *
   7  * This code is derived from software contributed to The NetBSD Foundation
   8  * by UCHIYAMA Yasushi.
   9  *
  10  * Redistribution and use in source and binary forms, with or without
  11  * modification, are permitted provided that the following conditions
  12  * are met:
  13  * 1. Redistributions of source code must retain the above copyright
  14  *    notice, this list of conditions and the following disclaimer.
  15  * 2. Redistributions in binary form must reproduce the above copyright
  16  *    notice, this list of conditions and the following disclaimer in the
  17  *    documentation and/or other materials provided with the distribution.
  18  *
  19  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
  20  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  21  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  22  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  23  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  29  * POSSIBILITY OF SUCH DAMAGE.
  30  */
  31
  32 /*
  33  *  TOSHIBA TMPR3912/3922 interrupt module.
  34  */
  35 #ifdef TX391X
  36 #define TX39_INTRSET_MAX        5
  37 #endif /* TX391X */
  38 #ifdef TX392X
  39 #define TX39_INTRSET_MAX        8
  40 #endif /* TX391X */
  41
  42 #define TX39_IRQHIGH_MAX        16
  43 /* R */
  44 #define TX39_INTRSTATUS1_REG    0x100
  45 #define TX39_INTRSTATUS2_REG    0x104
  46 #define TX39_INTRSTATUS3_REG    0x108
  47 #define TX39_INTRSTATUS4_REG    0x10c
  48 #define TX39_INTRSTATUS5_REG    0x110
  49 #define TX39_INTRSTATUS6_REG    0x114
  50 #ifdef TX392X
  51 #define TX39_INTRSTATUS7_REG    0x130
  52 #define TX39_INTRSTATUS8_REG    0x138
  53 #endif /* TX392X */
  54 #ifdef TX391X
  55 #define TX39_INTRSTATUS_REG(x)  (((x) - 1) * 4 + TX39_INTRSTATUS1_REG)
  56 #endif /* TX391X */
  57 #ifdef TX392X
  58 #define TX39_INTRSTATUS_REG(x)  (((x) <= 6) ?                           \
  59         (((x) - 1) * 4 + TX39_INTRSTATUS1_REG) :                        \
  60         (((x) - 7) * 8 + TX39_INTRSTATUS7_REG))
  61 #endif /* TX392X */
  62
  63 /* W */
  64 #define TX39_INTRCLEAR1_REG     0x100
  65 #define TX39_INTRCLEAR2_REG     0x104
  66 #define TX39_INTRCLEAR3_REG     0x108
  67 #define TX39_INTRCLEAR4_REG     0x10c
  68 #define TX39_INTRCLEAR5_REG     0x110
  69 #ifdef TX392X
  70 #define TX39_INTRCLEAR7_REG     0x130
  71 #define TX39_INTRCLEAR8_REG     0x138
  72 #endif /* TX392X */
  73 #ifdef TX391X
  74 #define TX39_INTRCLEAR_REG(x)   (((x) - 1) * 4 + TX39_INTRCLEAR1_REG)
  75 #endif /* TX391X */
  76 #ifdef TX392X
  77 #define TX39_INTRCLEAR_REG(x)   (((x) <= 6) ?                           \
  78         (((x) - 1) * 4 + TX39_INTRCLEAR1_REG) :                         \
  79         (((x) - 7) * 8 + TX39_INTRCLEAR7_REG))
  80 #endif /* TX392X */
  81
  82 /* R/W */
  83 #define TX39_INTRENABLE1_REG    0x118
  84 #define TX39_INTRENABLE2_REG    0x11c
  85 #define TX39_INTRENABLE3_REG    0x120
  86 #define TX39_INTRENABLE4_REG    0x124
  87 #define TX39_INTRENABLE5_REG    0x128
  88 #define TX39_INTRENABLE6_REG    0x12c
  89 #ifdef TX392X
  90 #define TX39_INTRENABLE7_REG    0x134
  91 #define TX39_INTRENABLE8_REG    0x13c
  92 #endif /* TX392X */
  93 #ifdef TX391X
  94 #define TX39_INTRENABLE_REG(x)  (((x) - 1) * 4 + TX39_INTRENABLE1_REG)
  95 #endif /* TX391X */
  96 #ifdef TX392X
  97 #define TX39_INTRENABLE_REG(x)  (((x) <= 6) ?                           \
  98         (((x) - 1) * 4 + TX39_INTRENABLE1_REG) :                        \
  99         (((x) - 7) * 8 + TX39_INTRENABLE7_REG))
 100 #endif /* TX392X */
 101 /*
 102  *      IRQLOW
 103  */
 104 /*
 105  *      Interrupt status/clear 1 register.
 106  *                -> Enable 1 register
 107  */
 108 /* R/W */
 109 #ifdef TX391X
 110 #define TX39_INTRSTATUS1_LCDINT         0x80000000
 111 #define TX39_INTRSTATUS1_DFINT          0x40000000
 112 #endif /* TX391X */
 113 #define TX39_INTRSTATUS1_CHI0_5INT      0x20000000
 114 #define TX39_INTRSTATUS1_CHI1_0INT      0x10000000
 115 #define TX39_INTRSTATUS1_CHIDMACNTINT   0x08000000
 116 #define TX39_INTRSTATUS1_CHININTA       0x04000000
 117 #define TX39_INTRSTATUS1_CHININTB       0x02000000
 118 #define TX39_INTRSTATUS1_CHIACTINT      0x01000000
 119 #define TX39_INTRSTATUS1_CHIERRINT      0x00800000
 120 #define TX39_INTRSTATUS1_SND0_5INT      0x00400000
 121 #define TX39_INTRSTATUS1_SND1_0INT      0x00200000
 122 #define TX39_INTRSTATUS1_TEL0_5INT      0x00100000
 123 #define TX39_INTRSTATUS1_TEL1_0INT      0x00080000
 124 #define TX39_INTRSTATUS1_SNDDMACNTINT   0x00040000
 125 #define TX39_INTRSTATUS1_TELDMACNTINT   0x00020000
 126 #define TX39_INTRSTATUS1_LSNDCLIPINT    0x00010000
 127 #define TX39_INTRSTATUS1_RSNDCLIPINT    0x00008000
 128 #define TX39_INTRSTATUS1_VALSNDPOSINT   0x00004000
 129 #define TX39_INTRSTATUS1_VALSNDNEGINT   0x00002000
 130 #define TX39_INTRSTATUS1_VALTELPOSINT   0x00001000
 131 #define TX39_INTRSTATUS1_VALTELNEGINT   0x00000800
 132 #define TX39_INTRSTATUS1_SNDININT       0x00000400
 133 #define TX39_INTRSTATUS1_TELININT       0x00000200
 134 #define TX39_INTRSTATUS1_SIBSF0INT      0x00000100
 135 #define TX39_INTRSTATUS1_SIBSF1INT      0x00000080
 136 #define TX39_INTRSTATUS1_SIBIRQPOSINT   0x00000040
 137 #define TX39_INTRSTATUS1_SIBIRQNEGINT   0x00000020
 138
 139 #ifdef TX391X
 140 #define TX39_INTRSTATUS1_VIDEO          0xc0000000
 141 #endif /* TX391X */
 142 #define TX39_INTRSTATUS1_CHI            0x3f800000
 143 #define TX39_INTRSTATUS1_SND            0x007ffe00
 144 #define TX39_INTRSTATUS1_SIB            0x000001e0
 145
 146 /*
 147  *      Interrupt status/clear 2 register.
 148  *                -> Enable 2 register
 149  */
 150 /* R/W */
 151 #define TX39_INTRSTATUS2_UARTARXINT             0x80000000
 152 #define TX39_INTRSTATUS2_UARTARXOVERRUNINT      0x40000000
 153 #define TX39_INTRSTATUS2_UARTAFRAMEERRINT       0x20000000
 154 #define TX39_INTRSTATUS2_UARTABREAKINT          0x10000000
 155 #define TX39_INTRSTATUS2_UARTAPARITYERRINT      0x08000000
 156 #define TX39_INTRSTATUS2_UARTATXINT             0x04000000
 157 #define TX39_INTRSTATUS2_UARTATXOVERRUNINT      0x02000000
 158 #define TX39_INTRSTATUS2_UARTAEMPTYINT          0x01000000
 159 #define TX39_INTRSTATUS2_UARTADMAFULLINT        0x00800000
 160 #define TX39_INTRSTATUS2_UARTADMAHALFINT        0x00400000
 161
 162 #define TX39_INTRSTATUS2_UARTBRXINT             0x00200000
 163 #define TX39_INTRSTATUS2_UARTBRXOVERRUNINT      0x00100000
 164 #define TX39_INTRSTATUS2_UARTBFRAMEERRINT       0x00080000
 165 #define TX39_INTRSTATUS2_UARTBBREAKINT          0x00040000
 166 #define TX39_INTRSTATUS2_UARTBPARITYERRINT      0x00020000
 167 #define TX39_INTRSTATUS2_UARTBTXINT             0x00010000
 168 #define TX39_INTRSTATUS2_UARTBTXOVERRUNINT      0x00008000
 169 #define TX39_INTRSTATUS2_UARTBEMPTYINT          0x00004000
 170 #define TX39_INTRSTATUS2_UARTBDMAFULLINT        0x00002000
 171 #define TX39_INTRSTATUS2_UARTBDMAHALFINT        0x00001000
 172
 173 #define TX39_INTRSTATUS2_UARTRXINT(x)                                   \
 174         ((x) ? TX39_INTRSTATUS2_UARTBRXINT :                            \
 175          TX39_INTRSTATUS2_UARTARXINT)
 176 #define TX39_INTRSTATUS2_UARTRXOVERRUNINT(x)                            \
 177         ((x) ? TX39_INTRSTATUS2_UARTBRXOVERRUNINT :                     \
 178          TX39_INTRSTATUS2_UARTARXOVERRUNINT)
 179 #define TX39_INTRSTATUS2_UARTFRAMEERRINT(x)                             \
 180         ((x) ? TX39_INTRSTATUS2_UARTBFRAMEERRINT :                      \
 181          TX39_INTRSTATUS2_UARTAFRAMEERRINT)
 182 #define TX39_INTRSTATUS2_UARTBREAKINT(x)                                \
 183         ((x) ? TX39_INTRSTATUS2_UARTBBREAKINT :                         \
 184         TX39_INTRSTATUS2_UARTABREAKINT)
 185 #define TX39_INTRSTATUS2_UARTPARITYERRINT(x)                            \
 186         ((x) ? TX39_INTRSTATUS2_UARTBPARITYERRINT :                     \
 187          TX39_INTRSTATUS2_UARTAPARITYERRINT)
 188 #define TX39_INTRSTATUS2_UARTTXINT(x)                                   \
 189         ((x) ? TX39_INTRSTATUS2_UARTBTXINT :                            \
 190         TX39_INTRSTATUS2_UARTATXINT)
 191 #define TX39_INTRSTATUS2_UARTTXOVERRUNINT(x)                            \
 192         ((x) ? TX39_INTRSTATUS2_UARTBTXOVERRUNINT :                     \
 193         TX39_INTRSTATUS2_UARTATXOVERRUNINT)
 194 #define TX39_INTRSTATUS2_UARTEMPTYINT(x)                                \
 195         ((x) ? TX39_INTRSTATUS2_UARTBEMPTYINT :                         \
 196         TX39_INTRSTATUS2_UARTEMPTYINT)
 197 #define TX39_INTRSTATUS2_UARTDMAFULLINT(x)                              \
 198         ((x) ? TX39_INTRSTATUS2_UARTBDMAFULLINT :                       \
 199         TX39_INTRSTATUS2_UARTADMAFULLINT)
 200 #define TX39_INTRSTATUS2_UARTDMAHALFINT(x)                              \
 201         ((x) ? TX39_INTRSTATUS2_UARTBDMAHALFINT :                       \
 202         TX39_INTRSTATUS2_UARTADMAHALFINT)
 203
 204 #ifdef TX391X
 205 #define TX39_INTRSTATUS2_MBUSTXBUFAVAILINT      0x00000800
 206 #define TX39_INTRSTATUS2_MBUSTXERRINT           0x00000400
 207 #define TX39_INTRSTATUS2_MBUSEMPTYINT           0x00000200
 208 #define TX39_INTRSTATUS2_MBUSRXBUFAVAILINT      0x00000100
 209 #define TX39_INTRSTATUS2_MBUSRXERRINT           0x00000080
 210 #define TX39_INTRSTATUS2_MBUSDETINT             0x00000040
 211 #define TX39_INTRSTATUS2_MBUSDMAFULLINT         0x00000020
 212 #define TX39_INTRSTATUS2_MBUSDMAHALFINT         0x00000010
 213 #define TX39_INTRSTATUS2_MBUSPOSINT             0x00000008
 214 #define TX39_INTRSTATUS2_MBUSNEGINT             0x00000004
 215 #endif /* TX391X */
 216
 217 #define TX39_INTRSTATUS2_UARTA                  0xffc00000
 218 #define TX39_INTRSTATUS2_UARTB                  0x003ff000
 219 #ifdef TX391X
 220 #define TX39_INTRSTATUS2_MBUS                   0x00000ffc
 221 #endif /* TX391X */
 222 /*
 223  *      Interrupt status/clear 3 register. (Multifunction I/O pin)
 224  *                -> Enable 3 register
 225  */
 226 /* R/W */
 227 #define TX39_INTRSTATUS3_MFIOPOSINT(r)  ((r) << 1)
 228
 229 #define TX39_INTRSTATUS3_CHIFSPOSINT            0x80000000
 230 #define TX39_INTRSTATUS3_CHICLKPOSINT           0x40000000
 231 #define TX39_INTRSTATUS3_CHIDOUTPOSINT          0x20000000
 232 #define TX39_INTRSTATUS3_CHIDINPOSINT           0x10000000
 233 #define TX39_INTRSTATUS3_DREQPOSINT             0x08000000
 234 #define TX39_INTRSTATUS3_DGRINTPOSINT           0x04000000
 235 #define TX39_INTRSTATUS3_BC32KPOSINT            0x02000000
 236 #define TX39_INTRSTATUS3_TXDPOSINT              0x01000000
 237 #define TX39_INTRSTATUS3_RXDPOSINT              0x00800000
 238 #define TX39_INTRSTATUS3_CS1POSINT              0x00400000
 239 #define TX39_INTRSTATUS3_CS2POSINT              0x00200000
 240 #define TX39_INTRSTATUS3_CS3POSINT              0x00100000
 241 #define TX39_INTRSTATUS3_MCS0POSINT             0x00080000
 242 #define TX39_INTRSTATUS3_MCS1POSINT             0x00040000
 243 #define TX39_INTRSTATUS3_MCS2POSINT             0x00020000
 244 #define TX39_INTRSTATUS3_MCS3POSINT             0x00010000
 245 #define TX39_INTRSTATUS3_SPICLKPOSINT           0x00008000
 246 #define TX39_INTRSTATUS3_SPIOUTPOSINT           0x00004000
 247 #define TX39_INTRSTATUS3_SPINPOSINT             0x00002000
 248 #define TX39_INTRSTATUS3_SIBMCLKPOSINT          0x00001000
 249 #define TX39_INTRSTATUS3_CARDREGPOSINT          0x00000800
 250 #define TX39_INTRSTATUS3_CARDIOWRPOSINT         0x00000400
 251 #define TX39_INTRSTATUS3_CARDIORDPOSINT         0x00000200
 252 #define TX39_INTRSTATUS3_CARD1CSLPOSINT         0x00000100
 253 #define TX39_INTRSTATUS3_CARD1CSHPOSINT         0x00000080
 254 #define TX39_INTRSTATUS3_CARD2CSLPOSINT         0x00000040
 255 #define TX39_INTRSTATUS3_CARD2CSHPOSINT         0x00000020
 256 #define TX39_INTRSTATUS3_CARD1WAITPOSINT        0x00000010
 257 #define TX39_INTRSTATUS3_CARD2WAITPOSINT        0x00000008
 258 #define TX39_INTRSTATUS3_CARDDIRPOSINT          0x00000004
 259
 260 /*
 261  *      Interrupt status/clear 4 register. (Multifunction I/O pin)
 262  *                -> Enable 4 register
 263  */
 264 /* R/W */
 265 #define TX39_INTRSTATUS4_MFIONEGINT(r)  ((r) << 1)
 266
 267 #define TX39_INTRSTATUS4_CHIFSNEGINT            0x80000000
 268 #define TX39_INTRSTATUS4_CHICLKNEGINT           0x40000000
 269 #define TX39_INTRSTATUS4_CHIDOUTNEGINT          0x20000000
 270 #define TX39_INTRSTATUS4_CHIDINNEGINT           0x10000000
 271 #define TX39_INTRSTATUS4_DREQNEGINT             0x08000000
 272 #define TX39_INTRSTATUS4_DGRINTNEGINT           0x04000000
 273 #define TX39_INTRSTATUS4_BC32KNEGINT            0x02000000
 274 #define TX39_INTRSTATUS4_TXDNEGINT              0x01000000
 275 #define TX39_INTRSTATUS4_RXDNEGINT              0x00800000
 276 #define TX39_INTRSTATUS4_CS1NEGINT              0x00400000
 277 #define TX39_INTRSTATUS4_CS2NEGINT              0x00200000
 278 #define TX39_INTRSTATUS4_CS3NEGINT              0x00100000
 279 #define TX39_INTRSTATUS4_MCS0NEGINT             0x00080000
 280 #define TX39_INTRSTATUS4_MCS1NEGINT             0x00040000
 281 #define TX39_INTRSTATUS4_MCS2NEGINT             0x00020000
 282 #define TX39_INTRSTATUS4_MCS3NEGINT             0x00010000
 283 #define TX39_INTRSTATUS4_SPICLKNEGINT           0x00008000
 284 #define TX39_INTRSTATUS4_SPIOUTNEGINT           0x00004000
 285 #define TX39_INTRSTATUS4_SPINNEGINT             0x00002000
 286 #define TX39_INTRSTATUS4_SIBMCLKNEGINT          0x00001000
 287 #define TX39_INTRSTATUS4_CARDREGNEGINT          0x00000800
 288 #define TX39_INTRSTATUS4_CARDIOWRNEGINT         0x00000400
 289 #define TX39_INTRSTATUS4_CARDIORDNEGINT         0x00000200
 290 #define TX39_INTRSTATUS4_CARD1CSLNEGINT         0x00000100
 291 #define TX39_INTRSTATUS4_CARD1CSHNEGINT         0x00000080
 292 #define TX39_INTRSTATUS4_CARD2CSLNEGINT         0x00000040
 293 #define TX39_INTRSTATUS4_CARD2CSHNEGINT         0x00000020
 294 #define TX39_INTRSTATUS4_CARD1WAITNEGINT        0x00000010
 295 #define TX39_INTRSTATUS4_CARD2WAITNEGINT        0x00000008
 296 #define TX39_INTRSTATUS4_CARDDIRNEGINT          0x00000004
 297
 298 /*
 299  *      Interrupt status/clear 5 register.
 300  *                -> Enable 5 register
 301  */
 302 /* R/W */
 303 #define TX39_INTRSTATUS5_RTCINT         0x80000000
 304 #define TX39_INTRSTATUS5_ALARMINT       0x40000000
 305 #define TX39_INTRSTATUS5_PERINT         0x20000000
 306 #define TX39_INTRSTATUS5_STPTIMERINT    0x10000000
 307 #define TX39_INTRSTATUS5_POSPWRINT      0x08000000
 308 #define TX39_INTRSTATUS5_NEGPWRINT      0x04000000
 309 #define TX39_INTRSTATUS5_POSPWROKINT    0x02000000
 310 #define TX39_INTRSTATUS5_NEGPWROKINT    0x01000000
 311 #define TX39_INTRSTATUS5_POSONBUTNINT   0x00800000
 312 #define TX39_INTRSTATUS5_NEGONBUTNINT   0x00400000
 313 #define TX39_INTRSTATUS5_SPIBUFAVAILINT 0x00200000
 314 #define TX39_INTRSTATUS5_SPIERRINT      0x00100000
 315 #define TX39_INTRSTATUS5_SPIRCVINT      0x00080000
 316 #define TX39_INTRSTATUS5_SPIEMPTYINT    0x00040000
 317 #define TX39_INTRSTATUS5_IRCONSMINT     0x00020000
 318 #define TX39_INTRSTATUS5_CARSTINT       0x00010000
 319 #define TX39_INTRSTATUS5_POSCARINT      0x00008000
 320 #define TX39_INTRSTATUS5_NEGCARINT      0x00004000
 321 #ifdef TX391X
 322 #define TX39_INTRSTATUS5_IOPOSINT6      0x00002000
 323 #define TX39_INTRSTATUS5_IOPOSINT5      0x00001000
 324 #define TX39_INTRSTATUS5_IOPOSINT4      0x00000800
 325 #define TX39_INTRSTATUS5_IOPOSINT3      0x00000400
 326 #define TX39_INTRSTATUS5_IOPOSINT2      0x00000200
 327 #define TX39_INTRSTATUS5_IOPOSINT1      0x00000100
 328 #define TX39_INTRSTATUS5_IOPOSINT0      0x00000080
 329 #define TX39_INTRSTATUS5_IONEGINT6      0x00000040
 330 #define TX39_INTRSTATUS5_IONEGINT5      0x00000020
 331 #define TX39_INTRSTATUS5_IONEGINT4      0x00000010
 332 #define TX39_INTRSTATUS5_IONEGINT3      0x00000008
 333 #define TX39_INTRSTATUS5_IONEGINT2      0x00000004
 334 #define TX39_INTRSTATUS5_IONEGINT1      0x00000002
 335 #define TX39_INTRSTATUS5_IONEGINT0      0x00000001
 336 #endif /* TX391X */
 337
 338 #define TX39_INTRSTATUS5_TIMER          0xe0000000
 339 #define TX39_INTRSTATUS5_POWER          0x1fc00000
 340 #define TX39_INTRSTATUS5_SPI            0x003c0000
 341 #define TX39_INTRSTATUS5_IR             0x0003c000
 342 #ifdef TX391X
 343 #define TX39_INTRSTATUS5_IO             0x00003fff
 344
 345 #define TX39_INTRSTATUS5_IOPOSINT_SHIFT 7
 346 #define TX39_INTRSTATUS5_IOPOSINT_MASK  0x7f
 347 #define TX39_INTRSTATUS5_IOPOSINT(cr)                                   \
 348         (((cr) >> TX39_INTRSTATUS5_IOPOSINT_SHIFT) &                    \
 349         TX39_INTRSTATUS5_IOPOSINT_MASK)
 350 #define TX39_INTRSTATUS5_IOPOSINT_SET(cr, val)                          \
 351         ((cr) | (((val) << TX39_INTRSTATUS5_IOPOSINT_SHIFT) &           \
 352         (TX39_INTRSTATUS5_IOPOSINT_MASK << TX39_INTRSTATUS5_IOPOSINT_SHIFT)))
 353
 354 #define TX39_INTRSTATUS5_IONEGINT_SHIFT 0
 355 #define TX39_INTRSTATUS5_IONEGINT_MASK  0x7f
 356 #define TX39_INTRSTATUS5_IONEGINT(cr)                                   \
 357         (((cr) >> TX39_INTRSTATUS5_IONEGINT_SHIFT) &                    \
 358         TX39_INTRSTATUS5_IONEGINT_MASK)
 359 #define TX39_INTRSTATUS5_IONEGINT_SET(cr, val)                          \
 360         ((cr) | (((val) << TX39_INTRSTATUS5_IONEGINT_SHIFT) &           \
 361         (TX39_INTRSTATUS5_IONEGINT_MASK << TX39_INTRSTATUS5_IONEGINT_SHIFT)))
 362 #endif /* TX391X */
 363 /*
 364  *      Interrupt status 6 register.
 365  */
 366 /* R */
 367 #define TX39_INTRSTATUS6_IRQHIGH        0x80000000
 368 #define TX39_INTRSTATUS6_IRQLOW         0x40000000
 369
 370 #define TX39_INTRSTATUS6_INTVECT_SHIFT  2
 371 #define TX39_INTRSTATUS6_INTVECT_MASK   0xf
 372 #define TX39_INTRSTATUS6_INTVECT(cr)                                    \
 373         (((cr) >> TX39_INTRSTATUS6_INTVECT_SHIFT) &                     \
 374         TX39_INTRSTATUS6_INTVECT_MASK)
 375
 376 /*
 377  *      Interrupt enable 6 register.
 378  */
 379 /* R/W */
 380 #define TX39_INTRENABLE6_GLOBALEN       0x00040000
 381
 382 #define TX39_INTRENABLE6_PRIORITYMASK_SHIFT     0
 383 #define TX39_INTRENABLE6_PRIORITYMASK_MASK      0xffff
 384 #define TX39_INTRENABLE6_PRIORITYMASK(cr)                               \
 385         (((cr) >> TX39_INTRENABLE6_PRIORITYMASK_SHIFT) &                \
 386         TX39_INTRENABLE6_PRIORITYMASK_MASK)
 387 #define TX39_INTRENABLE6_PRIORITYMASK_SET(cr, val)                      \
 388         ((cr) | (((val) << TX39_INTRENABLE6_PRIORITYMASK_SHIFT) &       \
 389         (TX39_INTRENABLE6_PRIORITYMASK_MASK <<                          \
 390         TX39_INTRENABLE6_PRIORITYMASK_SHIFT)))
 391
 392 #ifdef TX392X
 393 /*
 394  *      Interrupt Status 7 Register
 395  */
 396 #define TX3922_INTRSTATUS7_IRTXCINT             0x00100000
 397 #define TX3922_INTRSTATUS7_IRRXCINT             0x00080000
 398 #define TX3922_INTRSTATUS7_IRTXEINT             0x00040000
 399 #define TX3922_INTRSTATUS7_IRRXEINT             0x00020000
 400 #define TX3922_INTRSTATUS7_IRSIRPXINT           0x00010000
 401
 402 /*
 403  *      Interrupt Status 8 Register
 404  */
 405 #define TX39_INTRSTATUS8_IOPOSINT15     0x80000000
 406 #define TX39_INTRSTATUS8_IOPOSINT14     0x40000000
 407 #define TX39_INTRSTATUS8_IOPOSINT13     0x20000000
 408 #define TX39_INTRSTATUS8_IOPOSINT12     0x10000000
 409 #define TX39_INTRSTATUS8_IOPOSINT11     0x08000000
 410 #define TX39_INTRSTATUS8_IOPOSINT10     0x04000000
 411 #define TX39_INTRSTATUS8_IOPOSINT9      0x02000000
 412 #define TX39_INTRSTATUS8_IOPOSINT8      0x01000000
 413 #define TX39_INTRSTATUS8_IOPOSINT7      0x00800000
 414 #define TX39_INTRSTATUS8_IOPOSINT6      0x00400000
 415 #define TX39_INTRSTATUS8_IOPOSINT5      0x00200000
 416 #define TX39_INTRSTATUS8_IOPOSINT4      0x00100000
 417 #define TX39_INTRSTATUS8_IOPOSINT3      0x00080000
 418 #define TX39_INTRSTATUS8_IOPOSINT2      0x00040000
 419 #define TX39_INTRSTATUS8_IOPOSINT1      0x00020000
 420 #define TX39_INTRSTATUS8_IOPOSINT0      0x00010000
 421 #define TX39_INTRSTATUS8_IONEGINT15     0x00008000
 422 #define TX39_INTRSTATUS8_IONEGINT14     0x00004000
 423 #define TX39_INTRSTATUS8_IONEGINT13     0x00002000
 424 #define TX39_INTRSTATUS8_IONEGINT12     0x00001000
 425 #define TX39_INTRSTATUS8_IONEGINT11     0x00000800
 426 #define TX39_INTRSTATUS8_IONEGINT10     0x00000400
 427 #define TX39_INTRSTATUS8_IONEGINT9      0x00000200
 428 #define TX39_INTRSTATUS8_IONEGINT8      0x00000100
 429 #define TX39_INTRSTATUS8_IONEGINT7      0x00000080
 430 #define TX39_INTRSTATUS8_IONEGINT6      0x00000040
 431 #define TX39_INTRSTATUS8_IONEGINT5      0x00000020
 432 #define TX39_INTRSTATUS8_IONEGINT4      0x00000010
 433 #define TX39_INTRSTATUS8_IONEGINT3      0x00000008
 434 #define TX39_INTRSTATUS8_IONEGINT2      0x00000004
 435 #define TX39_INTRSTATUS8_IONEGINT1      0x00000002
 436 #define TX39_INTRSTATUS8_IONEGINT0      0x00000001
 437
 438 #define TX3922_INTRSTATUS8_IOPOSINT_SHIFT       16
 439 #define TX3922_INTRSTATUS8_IOPOSINT_MASK        0xffff
 440 #define TX3922_INTRSTATUS8_IOPOSINT(cr)                                 \
 441         (((cr) >> TX3922_INTRSTATUS8_IOPOSINT_SHIFT) &                  \
 442         TX3922_INTRSTATUS8_IOPOSINT_MASK)
 443 #define TX3922_INTRSTATUS8_IOPOSINT_SET(cr, val)                        \
 444         ((cr) | (((val) << TX3922_INTRSTATUS8_IOPOSINT_SHIFT) &         \
 445         (TX3922_INTRSTATUS8_IOPOSINT_MASK <<                            \
 446         TX3922_INTRSTATUS8_IOPOSINT_SHIFT)))
 447
 448 #define TX3922_INTRSTATUS8_IONEGINT_SHIFT       0
 449 #define TX3922_INTRSTATUS8_IONEGINT_MASK        0xffff
 450 #define TX3922_INTRSTATUS8_IONEGINT(cr)                                 \
 451         (((cr) >> TX3922_INTRSTATUS8_IONEGINT_SHIFT) &                  \
 452         TX3922_INTRSTATUS8_IONEGINT_MASK)
 453 #define TX3922_INTRSTATUS8_IONEGINT_SET(cr, val)                        \
 454         ((cr) | (((val) << TX3922_INTRSTATUS8_IONEGINT_SHIFT) &         \
 455         (TX3922_INTRSTATUS8_IONEGINT_MASK <<                            \
 456         TX3922_INTRSTATUS8_IONEGINT_SHIFT)))
 457
 458 #endif /* TX392X */
 459
 460 /*
 461  *      IRQHIGH (Priority level interrupt)
 462  */
 463 #ifdef TX391X
 464 #define TX39_INTRPRI15_PWROK_BIT                0x00008000
 465 #define TX39_INTRPRI14_TIMER_ALARM_BIT          0x00004000
 466 #define TX39_INTRPRI13_TIMER_PERIODIC_BIT       0x00002000
 467 #define TX39_INTRPRI12_MBUS_BIT                 0x00001000
 468 #define TX39_INTRPRI11_UARTARX_BIT              0x00000800
 469 #define TX39_INTRPRI10_UARTBRX_BIT              0x00000400
 470 #define TX39_INTRPRI9_MFIO19_18_17_16POS_BIT    0x00000200
 471 #define TX39_INTRPRI8_MFIO1_0_IO6_5POS_BIT      0x00000100
 472 #define TX39_INTRPRI7_MFIO19_18_17_16NEG_BIT    0x00000080
 473 #define TX39_INTRPRI6_MFIO1_0_IO6_5NEG_BIT      0x00000040
 474 #define TX39_INTRPRI5_MBUSDMAFULL_BIT           0x00000020
 475 #define TX39_INTRPRI4_SNDDMACNT_BIT             0x00000010
 476 #define TX39_INTRPRI3_TELDMACNT_BIT             0x00000008
 477 #define TX39_INTRPRI2_CHIDMACNT_BIT             0x00000004
 478 #define TX39_INTRPRI1_IO0POSNEG_BIT             0x00000002
 479 #define TX39_INTRPRI0_BIT                       0x00000001
 480
 481 #define TX39_INTRPRI15_PWROK                    15
 482 #define TX39_INTRPRI14_TIMER_ALARM              14
 483 #define TX39_INTRPRI13_TIMER_PERIODIC           13
 484 #define TX39_INTRPRI12_MBUS                     12
 485 #define TX39_INTRPRI11_UARTARX                  11
 486 #define TX39_INTRPRI10_UARTBRX                  10
 487 #define TX39_INTRPRI9_MFIO19_18_17_16POS        9
 488 #define TX39_INTRPRI8_MFIO1_0_IO6_5POS          8
 489 #define TX39_INTRPRI7_MFIO19_18_17_16NEG        7
 490 #define TX39_INTRPRI6_MFIO1_0_IO6_5NEG          6
 491 #define TX39_INTRPRI5_MBUSDMAFULL               5
 492 #define TX39_INTRPRI4_SNDDMACNT                 4
 493 #define TX39_INTRPRI3_TELDMACNT                 3
 494 #define TX39_INTRPRI2_CHIDMACNT                 2
 495 #define TX39_INTRPRI1_IO0POSNEG                 1
 496 #define TX39_INTRPRI0                           0
 497 #endif /* TX391X */
 498
 499 #ifdef TX392X
 500 #define TX39_INTRPRI15_PWROK_BIT                0x00008000
 501 #define TX39_INTRPRI14_TIMER_ALARM_BIT          0x00004000
 502 #define TX39_INTRPRI13_TIMER_PERIODIC_BIT       0x00002000
 503 #define TX39_INTRPRI12_UARTABRX_BIT             0x00001000
 504 #define TX39_INTRPRI11_MFIO19_18_17_16POS_BIT   0x00000800
 505 #define TX39_INTRPRI10_MFIO1_0_IO6_5POS_BIT     0x00000400
 506 #define TX39_INTRPRI9_MFIO19_18_17_16NEG_BIT    0x00000200
 507 #define TX39_INTRPRI8_MFIO1_0_IO6_5NEG_BIT      0x00000100
 508 #define TX39_INTRPRI5_MBUSDMAFULL_BIT           0x00000020
 509 #define TX39_INTRPRI4_SNDDMACNT_BIT             0x00000010
 510 #define TX39_INTRPRI3_TELDMACNT_BIT             0x00000008
 511 #define TX39_INTRPRI2_CHIDMACNT_BIT             0x00000004
 512 #define TX39_INTRPRI1_IO0POSNEG_BIT             0x00000002
 513 #define TX39_INTRPRI0_BIT                       0x00000001
 514
 515 #define TX39_INTRPRI15_PWROK                    15
 516 #define TX39_INTRPRI14_TIMER_ALARM              14
 517 #define TX39_INTRPRI13_TIMER_PERIODIC           13
 518 #define TX39_INTRPRI12_UARTABRX                 12
 519 #define TX39_INTRPRI11_MFIO19_18_17_16POS       11
 520 #define TX39_INTRPRI10_MFIO1_0_IO6_5POS         10
 521 #define TX39_INTRPRI9_MFIO19_18_17_16NEG        9
 522 #define TX39_INTRPRI8_MFIO1_0_IO6_5NEG          8
 523 #define TX39_INTRPRI5_IRRXCRXE                  5
 524 #define TX39_INTRPRI4_SNDDMACNT                 4
 525 #define TX39_INTRPRI3_TELDMACNT                 3
 526 #define TX39_INTRPRI2_CHIDMACNT                 2
 527 #define TX39_INTRPRI1_IO0POSNEG                 1
 528 #define TX39_INTRPRI0                           0
 529 #endif /* TX392X */
 530
 531 /*
 532  *      CPU connection
 533  */
 534 #define TX39_INTRIRQHIGH_MIPS_HARD_INT          4
 535 #define TX39_INTRIRQLOW_MIPS_HARD_INT           2