sys/arch/hpcmips/vr/cmureg.h

   1 /*      $NetBSD: cmureg.h,v 1.4 2001/09/28 10:25:15 sato Exp $  */
   2
   3 /*-
   4  * Copyright (c) 1999 SATO Kazumi. All rights reserved.
   5  * Copyright (c) 1999 PocketBSD Project. All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  * 3. All advertising materials mentioning features or use of this software
  16  *    must display the following acknowledgement:
  17  *      This product includes software developed by the PocketBSD project
  18  *      and its contributors.
  19  * 4. Neither the name of the project nor the names of its contributors
  20  *    may be used to endorse or promote products derived from this software
  21  *    without specific prior written permission.
  22  *
  23  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
  24  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  25  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  26  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  27  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  28  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  29  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  30  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  31  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  32  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  33  * SUCH DAMAGE.
  34  *
  35  */
  36
  37 /*
  38  *      CMU (CLock MASK UNIT) Registers.
  39  *              start 0x0B000060 (Vr4102-4111)
  40  *              start 0x0F000060 (Vr4122-4131)
  41  *              start 0x0A000004 (Vr4181)
  42  */
  43 #define CMUNOMASK                       0
  44
  45 #define CMUCLKMASK              0x000   /* CMU Clock Mask Register */
  46
  47 /* vr4102-4121 */
  48 #define         VR4102_CMUMSKPCIU       CMUNOMASK       /* no PCICLK */
  49 #define         VR4102_CMUMSKFFIR       (1<<10)         /* 1 supply 48MHz to FIR */
  50 #define         VR4102_CMUMSKSHSP       (1<<9)          /* 1 supply 18.432MHz to HSP */
  51 #define         VR4102_CMUMSKSSIU       (1<<8)          /* 1 supply 18.432MHz to SIU */
  52 #define         VR4102_CMUMSKDSIU       (1<<5)          /* 1 supply Tclock to DSIU */
  53 #define         VR4102_CMUMSKCSI        CMUNOMASK       /* no CSI clock */
  54 #define         VR4102_CMUMSKFIR        (1<<4)          /* 1 supply Tclock to FIR */
  55 #define         VR4102_CMUMSKKIU        (1<<3)          /* 1 supply Tclock to KIU */
  56 #define         VR4102_CMUMSKAIU        (1<<2)          /* 1 supply Tclock to AIU */
  57 #define         VR4102_CMUMSKSIU        (1<<1)          /* 1 supply Tclock to SIU */
  58 #define         VR4102_CMUMSKPIU        (1)             /* 1 supply Tclock to PIU */
  59
  60 /* vr4122-4131 */
  61 #define         VR4122_CMUMSKPCIU       ((1<<13)|(1<<7))        /* 1 supply PCICLK */
  62 #define         VR4122_CMUMSKSCSI       (1<<12)         /* 1 supply CSI 18.432MHz clock */
  63 #define         VR4122_CMUMSKDSIU       (1<<11)         /* 1 supply DSIU 18.432MHz clock */
  64 #define         VR4122_CMUMSKFFIR       (1<<10)         /* 1 supply 48MHz to FIR */
  65 #define         VR4122_CMUMSKSHSP       CMUNOMASK       /* no HSP */
  66 #define         VR4122_CMUMSKSSIU       (1<<8)          /* 1 supply 18.432MHz to SIU */
  67 #define         VR4122_CMUMSKCSI        (1<<6)          /* 1 supply Tclock to CSI */
  68 #define         VR4122_CMUMSKFIR        (1<<4)          /* 1 supply Tclock to FIR */
  69 #define         VR4122_CMUMSKKIU        CMUNOMASK       /* no KIU */
  70 #define         VR4122_CMUMSKAIU        CMUNOMASK       /* no AIU */
  71 #define         VR4122_CMUMSKSIU        (1<<1)          /* 1 supply Tclock to SIU */
  72 #define         VR4122_CMUMSKPIU        CMUNOMASK       /* no PIU */
  73
  74 /* vr4181 */
  75 #define         VR4181_CMUMSKPCIU       CMUNOMASK       /* no PCICLK */
  76 #define         VR4181_CMUMSKHSP        CMUNOMASK       /* no HSP */
  77 #define         VR4181_CMUMSKDSIU       CMUNOMASK       /* no DSIU */
  78 #define         VR4181_CMUMSKCSI        (1<<6)          /* 1 supply PCLK to CSI */
  79 #define         VR4181_CMUMSKFIR        CMUNOMASK       /* no FIR */
  80 #define         VR4181_CMUMSKKIU        CMUNOMASK       /* no KIU */
  81 #define         VR4181_CMUMSKAIU        (1<<5)          /* 1 supply PLCK to AIU */
  82 #define         VR4181_CMUMSKPIU        (1<<4)          /* 1 supply PLCK to PIU */
  83 #define         VR4181_CMUMSKADU        (1<<3)          /* 1 supply PLCK to ADU */
  84 #define         VR4181_CMUMSKSSIU       (1<<2)          /* 1 supply 18.432MHz to SIU */
  85 #define         VR4181_CMUMSKSADU       (1<<1)          /* 1 supply 18.432MHz to ADU */
  86
  87 #if defined SINGLE_VRIP_BASE
  88
  89 #ifdef VRGROUP_4102_4121
  90 #define CMUMASK_PIU     VR4102_CMUMSKPIU
  91 #define CMUMASK_SIU     (VR4102_CMUMSKSIU|VR4102_CMUMSKSSIU)
  92 #define CMUMASK_AIU     VR4102_CMUMSKAIU
  93 #define CMUMASK_KIU     VR4102_CMUMSKKIU
  94 #define CMUMASK_FIR     (VR4102_CMUMSKFIR|VR4102_CMUMSKFFIR)
  95 #define CMUMASK_DSIU    VR4102_CMUMSKDSIU
  96 #define CMUMASK_HSP     VR4102_CMUMSKHSP
  97 #define CMUMASK_CSI     VR4102_CMUMSKCSI
  98 #define CMUMASK_PCIU    VR4102_CMUMSKPCIU
  99 #endif /* VRGROUP_4102_4121 */
 100
 101 #ifdef VRGROUP_4122_4131
 102 #define CMUMASK_PIU     VR4122_CMUMSKPIU
 103 #define CMUMASK_SIU     (VR4122_CMUMSKSIU|VR4122_CMUMSKSSIU)
 104 #define CMUMASK_AIU     VR4122_CMUMSKAIU
 105 #define CMUMASK_KIU     VR4122_CMUMSKKIU
 106 #define CMUMASK_FIR     (VR4122_CMUMSKFIR|VR4122_CMUMSKFFIR)
 107 #define CMUMASK_DSIU    VR4122_CMUMSKDSIU
 108 #define CMUMASK_HSP     VR4122_CMUMSKHSP
 109 #define CMUMASK_CSI     (VR4122_CMUMSKSCSI|VR4122_CMUMSKCSI)
 110 #define CMUMASK_PCIU    VR4122_CMUMSKPCIU
 111 #endif /* VRGROUP_4122_4131 */
 112
 113 #ifdef VRGROUP_4181
 114 #define CMUMASK_PIU     VR4181_CMUMSKPIU
 115 #define CMUMASK_SIU     VR4181_CMUMSKSSIU
 116 #define CMUMASK_AIU     (VR4181_CMUMSKAIU|VR4181_CMUMSKADU|VR4181_CMUMSKSADU)
 117 #define CMUMASK_KIU     VR4181_CMUMSKKIU
 118 #define CMUMASK_FIR     VR4181_CMUMSKFIR
 119 #define CMUMASK_DSIU    VR4181_CMUMSKDSIU
 120 #define CMUMASK_HSP     VR4181_CMUMSKHSP
 121 #define CMUMASK_CSI     VR4181_CMUMSKCSI
 122 #define CMUMASK_PCIU    VR4181_CMUMSKPCIU
 123 #endif /* VRGROUP_4181 */
 124
 125 #endif /* SINGLE_VRIP_BASE */
 126 /* END cmureg.h */