sys/arch/hppa/include/reg.h

   1 /*      $NetBSD: reg.h,v 1.9 2009/05/24 06:53:35 skrll Exp $    */
   2
   3 /*      $OpenBSD: reg.h,v 1.7 2000/06/15 17:00:37 mickey Exp $  */
   4
   5 /*
   6  * Copyright (c) 1998-2004 Michael Shalayeff
   7  * All rights reserved.
   8  *
   9  * Redistribution and use in source and binary forms, with or without
  10  * modification, are permitted provided that the following conditions
  11  * are met:
  12  * 1. Redistributions of source code must retain the above copyright
  13  *    notice, this list of conditions and the following disclaimer.
  14  * 2. Redistributions in binary form must reproduce the above copyright
  15  *    notice, this list of conditions and the following disclaimer in the
  16  *    documentation and/or other materials provided with the distribution.
  17  *
  18  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  19  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  20  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  21  * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT,
  22  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  23  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  24  * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  25  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  26  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
  27  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  28  * THE POSSIBILITY OF SUCH DAMAGE.
  29  */
  30 /*
  31  * Copyright (c) 1990,1994 The University of Utah and
  32  * the Computer Systems Laboratory at the University of Utah (CSL).
  33  * All rights reserved.
  34  *
  35  * Permission to use, copy, modify and distribute this software is hereby
  36  * granted provided that (1) source code retains these copyright, permission,
  37  * and disclaimer notices, and (2) redistributions including binaries
  38  * reproduce the notices in supporting documentation, and (3) all advertising
  39  * materials mentioning features or use of this software display the following
  40  * acknowledgement: ``This product includes software developed by the
  41  * Computer Systems Laboratory at the University of Utah.''
  42  *
  43  * THE UNIVERSITY OF UTAH AND CSL ALLOW FREE USE OF THIS SOFTWARE IN ITS "AS
  44  * IS" CONDITION.  THE UNIVERSITY OF UTAH AND CSL DISCLAIM ANY LIABILITY OF
  45  * ANY KIND FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
  46  *
  47  * CSL requests users of this software to return to csl-dist@cs.utah.edu any
  48  * improvements that they make and grant CSL redistribution rights.
  49  *
  50  *      Utah $Hdr: regs.h 1.6 94/12/14$
  51  *      Author: Bob Wheeler, University of Utah CSL
  52  */
  53
  54 #ifndef _HPPA_REG_H_
  55 #define _HPPA_REG_H_
  56
  57 /*
  58  * constants for registers for use with the following routines:
  59  *
  60  *     void mtctl(reg, value)   - move to control register
  61  *     int mfctl(reg)           - move from control register
  62  *     int mtsp(sreg, value)    - move to space register
  63  *     int mfsr(sreg)           - move from space register
  64  */
  65
  66 #define CR_RCTR         0
  67 #define CR_PIDR1        8
  68 #define CR_PIDR2        9
  69 #define CR_CCR          10
  70 #define CR_SAR          11
  71 #define CR_PIDR3        12
  72 #define CR_PIDR4        13
  73 #define CR_IVA          14
  74 #define CR_EIEM         15
  75 #define CR_ITMR         16
  76 #define CR_PCSQ         17
  77 #define CR_PCOQ         18
  78 #define CR_IIR          19
  79 #define CR_ISR          20
  80 #define CR_IOR          21
  81 #define CR_IPSW         22
  82 #define CR_EIRR         23
  83
  84 /* Temporary control registers */
  85 #define CR_CURLWP       24      /* tr0: curlwp                          */
  86 #define CR_VTOP         25      /* tr1: virt to phys table address      */
  87 #define CR_TR2          26      /* tr2: temporary                       */
  88 #define CR_TLS          27      /* tr3: thread local storage pointer    */
  89 #define CR_HVTP         28      /* tr4: faulted HVT slot ptr on LC cpus */
  90 #define CR_TR5          29      /* tr5: emu / TLB_STATS_{PRE,AFT}       */
  91 #define CR_UPADDR       30      /* tr6: paddr of U-area of curlwp       */
  92 #define CR_TR7          31      /* tr7: trap temporary register         */
  93
  94 /*
  95  * Diagnostic registers and bit positions
  96  */
  97 #define DR_CPUCFG               0
  98
  99 #define DR0_PCXS_DHPMC          10      /* r/c D-cache error flag */
 100 #define DR0_PCXS_ILPMC          14      /* r/c I-cache error flag */
 101 #define DR0_PCXS_EQWSTO         16      /* r/w enable quad-word stores */
 102 #define DR0_PCXS_IHE            18      /* r/w I-cache sid hash enable */
 103 #define DR0_PCXS_DOMAIN         19
 104 #define DR0_PCXS_DHE            20      /* r/w D-cache sid hash enable */
 105
 106 #define DR0_PCXT_DHPMC          10      /* r/c L1 D-cache error flag */
 107 #define DR0_PCXT_ILPMC          14      /* r/c L1 I-cache error flag */
 108 #define DR0_PCXT_IHE            18      /* r/w I-cache sid hash enable */
 109 #define DR0_PCXT_DHE            20      /* r/w D-cache sid hash enable */
 110
 111 /* Bits in CPU Diagnose Register 0 */
 112 #define DR0_PCXL_L2IHPMC        6       /* r/c L2 I-cache error flag */
 113 #define DR0_PCXL_L2IHPMC_DIS    7       /* r/w L2 I-cache hpmc disable mask */
 114 #define DR0_PCXL_L2DHPMC        8       /* r/c L2 D-cache error flag */
 115 #define DR0_PCXL_L2DHPMC_DIS    9       /* r/w L2 D-cache hpmc disable mask */
 116 #define DR0_PCXL_L1IHPMC        10      /* r/c L1 I-cache error flag */
 117 #define DR0_PCXL_L1IHPMC_DIS    11      /* r/w L1 I-cache hpmc disable mask */
 118 #define DR0_PCXL_L2PARERR       15      /* r/c L2 Cache parity error (4 bit) */
 119 #define DR0_PCXL_STORE0         16      /* r/w scratch space */
 120 #define DR0_PCXL_PFMASK         17      /* r/w power-fail trap mask */
 121 #define DR0_PCXL_STORE1         18      /* r/w scratch */
 122 #define DR0_PCXL_FASTMODE       19      /* r   0-fast, 1-slow */
 123 #define DR0_PCXL_ISTRM_EN       20      /* r/w I-cache streaming enable */
 124 #define DR0_PCXL_DUAL_DIS       22      /* r/w disable dual-issue (2 bit) */
 125 #define DR0_PCXL_ENDIAN         23      /* r/w little endian traps */
 126 #define DR0_PCXL_SOU_EN         24      /* r/w stall-on-use on dc misses */
 127 #define DR0_PCXL_SHINT_EN       25      /* r/w no-fill on miss store hints */
 128 #define DR0_PCXL_IPREF_EN       26      /* r/w L2 to L1 I-cache prefetch */
 129 #define DR0_PCXL_L2DHASH_EN     27      /* r/w L2 D-cache hash enable */
 130 #define DR0_PCXL_L2IHASH_EN     28      /* r/w L2 I-cache hash enable */
 131 #define DR0_PCXL_L1ICACHE_EN    29      /* r/w L1 I-cache enable */
 132 #define DR0_PCXL_HIT            30      /* r   Diag cache read hit indication */
 133 #define DR0_PCXL_PARERR         31      /* r   Diag cache read parity error */
 134
 135 /* Bits in CPU Diagnose Register 25 */
 136 #define DR25_PCXL_POWFAIL       31      /* r   set to 0 by HW on PWR fail */
 137
 138 #define DR0_PCXL2_L1DHPMC       8       /* r/c L1 D-cache error flag */
 139 #define DR0_PCXL2_L1DHPMC_DIS   9       /* r/w L1 D-cache hpmc disable */
 140 #define DR0_PCXL2_L2DHPMC       10      /* r/c L1 I-cache error flag */
 141 #define DR0_PCXL2_L2DHPMC_DIS   11      /* r/w L1 I-cache hpmc disable */
 142 #define DR0_PCXL2_SCRATCH       12      /* r/w scratch register */
 143 #define DR0_PCXL2_ACCEL_IO      13      /*  /w enable accel IO writes */
 144 #define DR0_PCXL2_STORE0        16      /* r/w scratch space */
 145 #define DR0_PCXL2_PFMASK        17      /* r/w power-fail trap mask */
 146 #define DR0_PCXL2_STORE1        18      /* r/w scratch */
 147 #define DR0_PCXL2_DCSAFE        19      /* r/w serialize all data cache hangs */
 148 #define DR0_PCXL2_ISTRM_EN      20      /* r/w I-cache streaming enable */
 149 #define DR0_PCXL2_DUAL_DIS      22      /* r/w disable dual-issue (2 bit) */
 150 #define DR0_PCXL2_ENDIAN        23      /* r/w little endian traps */
 151 #define DR0_PCXL2_SOU_EN        24      /* r/w stall-on-use on dc misses */
 152 #define DR0_PCXL2_SHINT_EN      25      /* r/w no-fill on miss store hints */
 153 #define DR0_PCXL2_IPREF_EN      26      /* r/w L2 to L1 I-cache prefetch */
 154 #define DR0_PCXL2_LMIN_EN       27      /* r/w minor ill insn traps on LIH */
 155 #define DR0_PCXL2_RMIN_EN       28      /* r/w major ill insn traps on RIH */
 156 #define DR0_PCXL2_L1CACHE_EN    29      /* r/w L1 I-cache enable */
 157
 158 #define DR_DTLB                 8
 159
 160 #define DR_ITLB                 9
 161
 162 #define DR0_PCXL2_HTLB_ADDR     24      /* page address of the htlb */
 163 #define DR0_PCXL2_HTLB_CFG      25      /* htlb config */
 164 #define DR0_PCXL2_HTLB_P        0       /* r   latches power fail signal */
 165 #define DR0_PCXL2_HTLB_MASK     19      /*   w 12bit mask of the hash */
 166 #define DR0_PCXL2_HTLB_FP       26      /* r/w 3bit FP delay */
 167 #define DR0_PCXL2_HTLB_I        28      /* r/w disable ITLB htlb lookup */
 168 #define DR0_PCXL2_HTLB_U        29      /* r/w set cr28 only if tag nomatch */
 169 #define DR0_PCXL2_HTLB_N        30      /* r/w set cr28 from w3 or w7 (0) */
 170 #define DR0_PCXL2_HTLB_D        31      /* r/w disable DTLB htlb lookup */
 171
 172 #define DR_ITLB_SIZE_1          24
 173 #define DR_ITLB_SIZE_0          25
 174
 175 #define DR_DTLB_SIZE_1          26
 176 #define DR_DTLB_SIZE_0          27
 177
 178 #define CCR_MASK 0xff
 179
 180 #define HPPA_NREGS      (32)
 181 #define HPPA_NFPREGS    (33)    /* 33rd is used for r0 in fpemul */
 182
 183 #ifndef __ASSEMBLER__
 184
 185 struct reg {
 186         uint32_t r_regs[HPPA_NREGS];    /* r0 is psw */
 187
 188         uint32_t r_sar;
 189
 190         uint32_t r_pcsqh;
 191         uint32_t r_pcsqt;
 192         uint32_t r_pcoqh;
 193         uint32_t r_pcoqt;
 194
 195         uint32_t r_sr0;
 196         uint32_t r_sr1;
 197         uint32_t r_sr2;
 198         uint32_t r_sr3;
 199         uint32_t r_sr4;
 200         uint32_t r_sr5; /* !mcontext */
 201         uint32_t r_sr6; /* !mcontext */
 202         uint32_t r_sr7; /* !mcontext */
 203
 204         uint32_t r_cr26;
 205         uint32_t r_cr27;
 206 };
 207
 208 struct fpreg {
 209         uint64_t fpr_regs[HPPA_NFPREGS];
 210 };
 211 #endif /* !__ASSEMBLER__ */
 212
 213 #endif /* _HPPA_REG_H_ */