sys/arch/ia64/include/fpu.h

   1 /*      $NetBSD$        */
   2
   3 /*-
   4  * Copyright (c) 1998 Doug Rabson
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  26  * SUCH DAMAGE.
  27  *
  28  * $FreeBSD$
  29  */
  30
  31 #ifndef _MACHINE_FPU_H_
  32 #define _MACHINE_FPU_H_
  33
  34 /*
  35  * Floating point status register bits.
  36  */
  37
  38 #define IA64_FPSR_TRAP_VD       0x0000000000000001L
  39 #define IA64_FPSR_TRAP_DD       0x0000000000000002L
  40 #define IA64_FPSR_TRAP_ZD       0x0000000000000004L
  41 #define IA64_FPSR_TRAP_OD       0x0000000000000008L
  42 #define IA64_FPSR_TRAP_UD       0x0000000000000010L
  43 #define IA64_FPSR_TRAP_ID       0x0000000000000020L
  44 #define IA64_FPSR_SF(i,v)       ((v) << ((i)*13+6))
  45
  46 #define IA64_SF_FTZ             0x0001L
  47 #define IA64_SF_WRE             0x0002L
  48 #define IA64_SF_PC              0x000cL
  49 #define IA64_SF_PC_0            0x0000L
  50 #define IA64_SF_PC_1            0x0004L
  51 #define IA64_SF_PC_2            0x0008L
  52 #define IA64_SF_PC_3            0x000cL
  53 #define IA64_SF_RC              0x0030L
  54 #define IA64_SF_RC_NEAREST      0x0000L
  55 #define IA64_SF_RC_NEGINF       0x0010L
  56 #define IA64_SF_RC_POSINF       0x0020L
  57 #define IA64_SF_RC_TRUNC        0x0030L
  58 #define IA64_SF_TD              0x0040L
  59 #define IA64_SF_V               0x0080L
  60 #define IA64_SF_D               0x0100L
  61 #define IA64_SF_Z               0x0200L
  62 #define IA64_SF_O               0x0400L
  63 #define IA64_SF_U               0x0800L
  64 #define IA64_SF_I               0x1000L
  65
  66 #define IA64_SF_DEFAULT         (IA64_SF_PC_3 | IA64_SF_RC_NEAREST)
  67
  68 #define IA64_FPSR_DEFAULT       (IA64_FPSR_TRAP_VD                      \
  69                                  | IA64_FPSR_TRAP_DD                    \
  70                                  | IA64_FPSR_TRAP_ZD                    \
  71                                  | IA64_FPSR_TRAP_OD                    \
  72                                  | IA64_FPSR_TRAP_UD                    \
  73                                  | IA64_FPSR_TRAP_ID                    \
  74                                  | IA64_FPSR_SF(0, IA64_SF_DEFAULT)     \
  75                                  | IA64_FPSR_SF(1, (IA64_SF_DEFAULT     \
  76                                                     | IA64_SF_TD        \
  77                                                     | IA64_SF_WRE))     \
  78                                  | IA64_FPSR_SF(2, (IA64_SF_DEFAULT     \
  79                                                     | IA64_SF_TD))      \
  80                                  | IA64_FPSR_SF(3, (IA64_SF_DEFAULT     \
  81                                                     | IA64_SF_TD)))
  82
  83 struct fpswa_ret {
  84         unsigned long   status;
  85         unsigned long   err1;
  86         unsigned long   err2;
  87         unsigned long   err3;
  88 };
  89
  90 struct fpswa_bundle {
  91         long double     bits;           /* Force 16-byte alignment. */
  92 };
  93
  94 struct fpswa_fpctx {
  95         unsigned long   mask_low;                       /* f63 - f2 */
  96         unsigned long   mask_high;                      /* f127 - f64 */
  97         union _ia64_fpreg *fp_low_preserved;            /* f2 - f5 */
  98         union _ia64_fpreg *fp_low_volatile;             /* f6 - f15 */
  99         union _ia64_fpreg *fp_high_preserved;           /* f16 - f31 */
 100         union _ia64_fpreg *fp_high_volatile;            /* f32 - f127 */
 101 };
 102
 103 struct fpswa_iface {
 104         unsigned int    if_rev;
 105         unsigned int    __res;
 106         struct fpswa_ret (*if_fpswa)(unsigned long, struct fpswa_bundle *,
 107             unsigned long *, unsigned long *, unsigned long *, unsigned long *,
 108             unsigned long *, struct fpswa_fpctx *);
 109 };
 110
 111 #endif /* ! _MACHINE_FPU_H_ */