sys/arch/ia64/include/ia64_cpu.h

   1 /*      $NetBSD: ia64_cpu.h,v 1.1 2006/04/07 14:21:18 cherry Exp $      */
   2
   3 /*-
   4  * Copyright (c) 2000 Doug Rabson
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  26  * SUCH DAMAGE.
  27  *
  28  *      $FreeBSD$
  29  */
  30
  31 #ifndef _MACHINE_IA64_CPU_H_
  32 #define _MACHINE_IA64_CPU_H_
  33
  34 /*
  35  * Definition of PSR and IPSR bits.
  36  */
  37 #define IA64_PSR_BE             0x0000000000000002
  38 #define IA64_PSR_UP             0x0000000000000004
  39 #define IA64_PSR_AC             0x0000000000000008
  40 #define IA64_PSR_MFL            0x0000000000000010
  41 #define IA64_PSR_MFH            0x0000000000000020
  42 #define IA64_PSR_IC             0x0000000000002000
  43 #define IA64_PSR_I              0x0000000000004000
  44 #define IA64_PSR_PK             0x0000000000008000
  45 #define IA64_PSR_DT             0x0000000000020000
  46 #define IA64_PSR_DFL            0x0000000000040000
  47 #define IA64_PSR_DFH            0x0000000000080000
  48 #define IA64_PSR_SP             0x0000000000100000
  49 #define IA64_PSR_PP             0x0000000000200000
  50 #define IA64_PSR_DI             0x0000000000400000
  51 #define IA64_PSR_SI             0x0000000000800000
  52 #define IA64_PSR_DB             0x0000000001000000
  53 #define IA64_PSR_LP             0x0000000002000000
  54 #define IA64_PSR_TB             0x0000000004000000
  55 #define IA64_PSR_RT             0x0000000008000000
  56 #define IA64_PSR_CPL            0x0000000300000000
  57 #define IA64_PSR_CPL_KERN       0x0000000000000000
  58 #define IA64_PSR_CPL_1          0x0000000100000000
  59 #define IA64_PSR_CPL_2          0x0000000200000000
  60 #define IA64_PSR_CPL_USER       0x0000000300000000
  61 #define IA64_PSR_IS             0x0000000400000000
  62 #define IA64_PSR_MC             0x0000000800000000
  63 #define IA64_PSR_IT             0x0000001000000000
  64 #define IA64_PSR_ID             0x0000002000000000
  65 #define IA64_PSR_DA             0x0000004000000000
  66 #define IA64_PSR_DD             0x0000008000000000
  67 #define IA64_PSR_SS             0x0000010000000000
  68 #define IA64_PSR_RI             0x0000060000000000
  69 #define IA64_PSR_RI_0           0x0000000000000000
  70 #define IA64_PSR_RI_1           0x0000020000000000
  71 #define IA64_PSR_RI_2           0x0000040000000000
  72 #define IA64_PSR_ED             0x0000080000000000
  73 #define IA64_PSR_BN             0x0000100000000000
  74 #define IA64_PSR_IA             0x0000200000000000
  75
  76 /*
  77  * Definition of ISR bits.
  78  */
  79 #define IA64_ISR_CODE           0x000000000000ffff
  80 #define IA64_ISR_VECTOR         0x0000000000ff0000
  81 #define IA64_ISR_X              0x0000000100000000
  82 #define IA64_ISR_W              0x0000000200000000
  83 #define IA64_ISR_R              0x0000000400000000
  84 #define IA64_ISR_NA             0x0000000800000000
  85 #define IA64_ISR_SP             0x0000001000000000
  86 #define IA64_ISR_RS             0x0000002000000000
  87 #define IA64_ISR_IR             0x0000004000000000
  88 #define IA64_ISR_NI             0x0000008000000000
  89 #define IA64_ISR_SO             0x0000010000000000
  90 #define IA64_ISR_EI             0x0000060000000000
  91 #define IA64_ISR_EI_0           0x0000000000000000
  92 #define IA64_ISR_EI_1           0x0000020000000000
  93 #define IA64_ISR_EI_2           0x0000040000000000
  94 #define IA64_ISR_ED             0x0000080000000000
  95
  96 /*
  97  * Vector numbers for various ia64 interrupts.
  98  */
  99 #define IA64_VEC_VHPT                   0
 100 #define IA64_VEC_ITLB                   1
 101 #define IA64_VEC_DTLB                   2
 102 #define IA64_VEC_ALT_ITLB               3
 103 #define IA64_VEC_ALT_DTLB               4
 104 #define IA64_VEC_NESTED_DTLB            5
 105 #define IA64_VEC_IKEY_MISS              6
 106 #define IA64_VEC_DKEY_MISS              7
 107 #define IA64_VEC_DIRTY_BIT              8
 108 #define IA64_VEC_INST_ACCESS            9
 109 #define IA64_VEC_DATA_ACCESS            10
 110 #define IA64_VEC_BREAK                  11
 111 #define IA64_VEC_EXT_INTR               12
 112 #define IA64_VEC_PAGE_NOT_PRESENT       20
 113 #define IA64_VEC_KEY_PERMISSION         21
 114 #define IA64_VEC_INST_ACCESS_RIGHTS     22
 115 #define IA64_VEC_DATA_ACCESS_RIGHTS     23
 116 #define IA64_VEC_GENERAL_EXCEPTION      24
 117 #define IA64_VEC_DISABLED_FP            25
 118 #define IA64_VEC_NAT_CONSUMPTION        26
 119 #define IA64_VEC_SPECULATION            27
 120 #define IA64_VEC_DEBUG                  29
 121 #define IA64_VEC_UNALIGNED_REFERENCE    30
 122 #define IA64_VEC_UNSUPP_DATA_REFERENCE  31
 123 #define IA64_VEC_FLOATING_POINT_FAULT   32
 124 #define IA64_VEC_FLOATING_POINT_TRAP    33
 125 #define IA64_VEC_LOWER_PRIVILEGE_TRANSFER 34
 126 #define IA64_VEC_TAKEN_BRANCH_TRAP      35
 127 #define IA64_VEC_SINGLE_STEP_TRAP       36
 128 #define IA64_VEC_IA32_EXCEPTION         45
 129 #define IA64_VEC_IA32_INTERCEPT         46
 130 #define IA64_VEC_IA32_INTERRUPT         47
 131
 132 /*
 133  * IA-32 exceptions.
 134  */
 135 #define IA32_EXCEPTION_DIVIDE           0
 136 #define IA32_EXCEPTION_DEBUG            1
 137 #define IA32_EXCEPTION_BREAK            3
 138 #define IA32_EXCEPTION_OVERFLOW         4
 139 #define IA32_EXCEPTION_BOUND            5
 140 #define IA32_EXCEPTION_DNA              7
 141 #define IA32_EXCEPTION_NOT_PRESENT      11
 142 #define IA32_EXCEPTION_STACK_FAULT      12
 143 #define IA32_EXCEPTION_GPFAULT          13
 144 #define IA32_EXCEPTION_FPERROR          16
 145 #define IA32_EXCEPTION_ALIGNMENT_CHECK  17
 146 #define IA32_EXCEPTION_STREAMING_SIMD   19
 147
 148 #define IA32_INTERCEPT_INSTRUCTION      0
 149 #define IA32_INTERCEPT_GATE             1
 150 #define IA32_INTERCEPT_SYSTEM_FLAG      2
 151 #define IA32_INTERCEPT_LOCK             4
 152
 153 #ifndef _LOCORE
 154
 155 /*
 156  * Various special ia64 instructions.
 157  */
 158
 159 /*
 160  * Memory Fence.
 161  */
 162 static __inline void
 163 ia64_mf(void)
 164 {
 165         __asm __volatile("mf");
 166 }
 167
 168 static __inline void
 169 ia64_mf_a(void)
 170 {
 171         __asm __volatile("mf.a");
 172 }
 173
 174 /*
 175  * Flush Cache.
 176  */
 177 static __inline void
 178 ia64_fc(uint64_t va)
 179 {
 180         __asm __volatile("fc %0" :: "r"(va));
 181 }
 182
 183 /*
 184  * Flush Instruction Cache
 185  */
 186
 187 static __inline void
 188 ia64_fc_i(uint64_t va)
 189 {
 190         __asm __volatile("fc.i %0" :: "r"(va));
 191 }
 192
 193 /*
 194  * Sync instruction stream.
 195  */
 196 static __inline void
 197 ia64_sync_i(void)
 198 {
 199         __asm __volatile("sync.i");
 200 }
 201
 202 /*
 203  * Calculate address in VHPT for va.
 204  */
 205 static __inline uint64_t
 206 ia64_thash(uint64_t va)
 207 {
 208         uint64_t result;
 209         __asm __volatile("thash %0=%1" : "=r" (result) : "r" (va));
 210         return result;
 211 }
 212
 213 /*
 214  * Calculate VHPT tag for va.
 215  */
 216 static __inline uint64_t
 217 ia64_ttag(uint64_t va)
 218 {
 219         uint64_t result;
 220         __asm __volatile("ttag %0=%1" : "=r" (result) : "r" (va));
 221         return result;
 222 }
 223
 224 /*
 225  * Convert virtual address to physical.
 226  */
 227 static __inline uint64_t
 228 ia64_tpa(uint64_t va)
 229 {
 230         uint64_t result;
 231         __asm __volatile("tpa %0=%1" : "=r" (result) : "r" (va));
 232         return result;
 233 }
 234
 235 /*
 236  * Generate a ptc.e instruction.
 237  */
 238 static __inline void
 239 ia64_ptc_e(uint64_t v)
 240 {
 241         __asm __volatile("ptc.e %0;; srlz.d;;" :: "r"(v));
 242 }
 243
 244 /*
 245  * Generate a ptc.g instruction.
 246  */
 247 static __inline void
 248 ia64_ptc_g(uint64_t va, uint64_t log2size)
 249 {
 250         __asm __volatile("ptc.g %0,%1;; srlz.d;;" :: "r"(va), "r"(log2size));
 251 }
 252
 253 /*
 254  * Generate a ptc.ga instruction.
 255  */
 256 static __inline void
 257 ia64_ptc_ga(uint64_t va, uint64_t log2size)
 258 {
 259         __asm __volatile("ptc.ga %0,%1;; srlz.d;;" :: "r"(va), "r"(log2size));
 260 }
 261
 262 /*
 263  * Generate a ptc.l instruction.
 264  */
 265 static __inline void
 266 ia64_ptc_l(uint64_t va, uint64_t log2size)
 267 {
 268         __asm __volatile("ptc.l %0,%1;; srlz.d;;" :: "r"(va), "r"(log2size));
 269 }
 270
 271 /*
 272  * Read the value of psr.
 273  */
 274 static __inline uint64_t
 275 ia64_get_psr(void)
 276 {
 277         uint64_t result;
 278         __asm __volatile("mov %0=psr;;" : "=r" (result));
 279         return result;
 280 }
 281
 282 /*
 283  * Define accessors for application registers.
 284  */
 285
 286 #define IA64_AR(name)                                           \
 287                                                                 \
 288 static __inline uint64_t                                        \
 289 ia64_get_##name(void)                                           \
 290 {                                                               \
 291         uint64_t result;                                        \
 292         __asm __volatile("mov %0=ar." #name : "=r" (result));   \
 293         return result;                                          \
 294 }                                                               \
 295                                                                 \
 296 static __inline void                                            \
 297 ia64_set_##name(uint64_t v)                                     \
 298 {                                                               \
 299         __asm __volatile("mov ar." #name "=%0;;" :: "r" (v));   \
 300 }
 301
 302 IA64_AR(k0)
 303 IA64_AR(k1)
 304 IA64_AR(k2)
 305 IA64_AR(k3)
 306 IA64_AR(k4)
 307 IA64_AR(k5)
 308 IA64_AR(k6)
 309 IA64_AR(k7)
 310
 311 IA64_AR(rsc)
 312 IA64_AR(bsp)
 313 IA64_AR(bspstore)
 314 IA64_AR(rnat)
 315
 316 IA64_AR(fcr)
 317
 318 IA64_AR(eflag)
 319 IA64_AR(csd)
 320 IA64_AR(ssd)
 321 IA64_AR(cflg)
 322 IA64_AR(fsr)
 323 IA64_AR(fir)
 324 IA64_AR(fdr)
 325
 326 IA64_AR(ccv)
 327
 328 IA64_AR(unat)
 329
 330 IA64_AR(fpsr)
 331
 332 IA64_AR(itc)
 333
 334 IA64_AR(pfs)
 335 IA64_AR(lc)
 336 IA64_AR(ec)
 337
 338 /*
 339  * Define accessors for control registers.
 340  */
 341
 342 #define IA64_CR(name)                                           \
 343                                                                 \
 344 static __inline uint64_t                                        \
 345 ia64_get_##name(void)                                           \
 346 {                                                               \
 347         uint64_t result;                                        \
 348         __asm __volatile("mov %0=cr." #name : "=r" (result));   \
 349         return result;                                          \
 350 }                                                               \
 351                                                                 \
 352 static __inline void                                            \
 353 ia64_set_##name(uint64_t v)                                     \
 354 {                                                               \
 355         __asm __volatile("mov cr." #name "=%0;;" :: "r" (v));   \
 356 }
 357
 358 IA64_CR(dcr)
 359 IA64_CR(itm)
 360 IA64_CR(iva)
 361
 362 IA64_CR(pta)
 363
 364 IA64_CR(ipsr)
 365 IA64_CR(isr)
 366
 367 IA64_CR(iip)
 368 IA64_CR(ifa)
 369 IA64_CR(itir)
 370 IA64_CR(iipa)
 371 IA64_CR(ifs)
 372 IA64_CR(iim)
 373 IA64_CR(iha)
 374
 375 IA64_CR(lid)
 376 IA64_CR(ivr)
 377 IA64_CR(tpr)
 378 IA64_CR(eoi)
 379 IA64_CR(irr0)
 380 IA64_CR(irr1)
 381 IA64_CR(irr2)
 382 IA64_CR(irr3)
 383 IA64_CR(itv)
 384 IA64_CR(pmv)
 385 IA64_CR(cmcv)
 386
 387 IA64_CR(lrr0)
 388 IA64_CR(lrr1)
 389
 390 /*
 391  * Write a region register.
 392  */
 393 static __inline void
 394 ia64_set_rr(uint64_t rrbase, uint64_t v)
 395 {
 396         __asm __volatile("mov rr[%0]=%1;; srlz.d;;"
 397                          :: "r"(rrbase), "r"(v) : "memory");
 398 }
 399
 400 /*
 401  * Read a CPUID register.
 402  */
 403 static __inline uint64_t
 404 ia64_get_cpuid(int i)
 405 {
 406         uint64_t result;
 407         __asm __volatile("mov %0=cpuid[%1]"
 408                          : "=r" (result) : "r"(i));
 409         return result;
 410 }
 411
 412 static __inline void
 413 ia64_disable_highfp(void)
 414 {
 415         __asm __volatile("ssm psr.dfh;; srlz.d");
 416 }
 417
 418 static __inline void
 419 ia64_enable_highfp(void)
 420 {
 421         __asm __volatile("rsm psr.dfh;; srlz.d");
 422 }
 423
 424 static __inline void
 425 ia64_srlz_d(void)
 426 {
 427         __asm __volatile("srlz.d");
 428 }
 429
 430 static __inline void
 431 ia64_srlz_i(void)
 432 {
 433         __asm __volatile("srlz.i;;");
 434 }
 435
 436 #endif /* !_LOCORE */
 437
 438 #endif /* _MACHINE_IA64_CPU_H_ */
 439