1 /* $NetBSD: intr.h,v 1.4 2008/03/20 09:09:20 kochi Exp $ */
3 /* XXX: cherry: To Be fixed when we switch on interrupts. */
8 #include <machine/intrdefs.h>
10 static __inline
int splraise(int dummy
) { return 0; }
11 static __inline
void spllower(int dummy
) { }
16 #define splvm() splraise(IPL_VM)
17 #define splhigh() splraise(IPL_HIGH)
18 #define spl0() spllower(IPL_NONE)
19 #define splsched() splraise(IPL_SCHED)
20 #define spllock() splhigh()
21 #define splx(x) spllower(x)
24 * Software interrupt masks
27 #define splsoftclock() splraise(IPL_SOFTCLOCK)
28 #define splsoftnet() splraise(IPL_SOFTNET)
29 #define splsoftserial() splraise(IPL_SOFTSERIAL)
36 static inline ipl_cookie_t
37 makeiplcookie(ipl_t ipl
)
40 return (ipl_cookie_t
){._ipl
= ipl
};
44 splraiseipl(ipl_cookie_t icookie
)
47 return splraise(icookie
._ipl
);
52 * Layout of the Processor Interrupt Block.
54 struct ia64_interrupt_block
56 uint64_t ib_ipi
[0x20000]; /* 1Mb of IPI interrupts */
57 uint8_t ib_reserved1
[0xe0000];
58 uint8_t ib_inta
; /* Generate INTA cycle */
59 uint8_t ib_reserved2
[7];
60 uint8_t ib_xtp
; /* XTP cycle */
61 uint8_t ib_reserved3
[7];
62 uint8_t ib_reserved4
[0x1fff0];
65 extern uint64_t ia64_lapic_address
;
67 #define IA64_INTERRUPT_BLOCK \
68 (struct ia64_interrupt_block *)IA64_PHYS_TO_RR6(ia64_lapic_address)
70 void *intr_establish(int, int, int, int (*)(void *), void *);
71 void intr_disestablish(void *);
73 #endif /* ! _IA64_INTR_H_ */