sys/arch/ia64/include/intrdefs.h

   1 /*      $NetBSD: intrdefs.h,v 1.2 2008/03/20 14:56:06 kochi Exp $       */
   2
   3 /*-
   4  * Copyright (c) 2008 The NetBSD Foundation, Inc.
   5  * All rights reserved.
   6  *
   7  * This code is derived from software contributed to The NetBSD Foundation
   8  * by Takayoshi Kochi.
   9  *
  10  * Redistribution and use in source and binary forms, with or without
  11  * modification, are permitted provided that the following conditions
  12  * are met:
  13  * 1. Redistributions of source code must retain the above copyright
  14  *    notice, this list of conditions and the following disclaimer.
  15  * 2. Redistributions in binary form must reproduce the above copyright
  16  *    notice, this list of conditions and the following disclaimer in the
  17  *    documentation and/or other materials provided with the distribution.
  18  *
  19  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
  20  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  21  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  22  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  23  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  29  * POSSIBILITY OF SUCH DAMAGE.
  30  */
  31
  32 #ifndef _IA64_INTRDEFS_H_
  33 #define _IA64_INTRDEFS_H_
  34
  35 /* Interrupt priority levels. */
  36 #define IPL_NONE        0x0     /* nothing */
  37 #define IPL_SOFTCLOCK   0x1     /* timeouts */
  38 #define IPL_SOFTBIO     0x2     /* block I/O passdown */
  39 #define IPL_SOFTNET     0x3     /* protocol stacks */
  40 #define IPL_SOFTSERIAL  0x4     /* serial passdown */
  41 #define IPL_VM          0x5     /* low I/O, memory allocation */
  42 #define IPL_SCHED       0x6     /* medium I/O, scheduler, clock */
  43 #define IPL_HIGH        0x7     /* high I/O, statclock, IPIs */
  44 #define NIPL            8
  45
  46 /* Interrupt sharing types. */
  47 #define IST_NONE        0       /* none */
  48 #define IST_PULSE       1       /* pulsed */
  49 #define IST_EDGE        2       /* edge-triggered */
  50 #define IST_LEVEL       3       /* level-triggered */
  51
  52 /*
  53  * Local APIC masks and software interrupt masks, in order
  54  * of priority.  Must not conflict with SIR_* below.
  55  */
  56 #define LIR_IPI         31
  57 #define LIR_TIMER       30
  58
  59 /*
  60  * XXX These should be lowest numbered, but right now would
  61  * conflict with the legacy IRQs.  Their current position
  62  * means that soft interrupt take priority over hardware
  63  * interrupts when lowering the priority level!
  64  */
  65 #define SIR_SERIAL      29
  66 #define SIR_NET         28
  67 #define SIR_BIO         27
  68 #define SIR_CLOCK       26
  69
  70 /*
  71  * Maximum # of interrupt sources per CPU. 32 to fit in one word.
  72  * ioapics can theoretically produce more, but it's not likely to
  73  * happen. For multiple ioapics, things can be routed to different
  74  * CPUs.
  75  */
  76 #define MAX_INTR_SOURCES        32
  77 #define NUM_LEGACY_IRQS         16
  78
  79 /*
  80  * Low and high boundaries between which interrupt gates will
  81  * be allocated in the IDT.
  82  */
  83 #define IDT_INTR_LOW    (0x20 + NUM_LEGACY_IRQS)
  84 #define IDT_INTR_HIGH   0xef
  85
  86 #define X86_IPI_HALT                    0x00000001
  87 #define X86_IPI_MICROSET                0x00000002
  88 #define X86_IPI_FLUSH_FPU               0x00000004
  89 #define X86_IPI_SYNCH_FPU               0x00000008
  90 #define X86_IPI_MTRR                    0x00000010
  91 #define X86_IPI_GDT                     0x00000020
  92 #define X86_IPI_WRITE_MSR               0x00000040
  93 #define X86_IPI_ACPI_CPU_SLEEP          0x00000080
  94
  95 #define X86_NIPI                8
  96
  97 #define X86_IPI_NAMES { "halt IPI", "timeset IPI", "FPU flush IPI", \
  98                          "FPU synch IPI", "MTRR update IPI", \
  99                          "GDT update IPI", "MSR write IPI", \
 100                          "ACPI CPU sleep IPI" }
 101
 102 #define IREENT_MAGIC    0x18041969
 103
 104 #endif /* _IA64_INTRDEFS_H_ */