6 device sbscd {[addr = -1], [intr[2] = {-1,-1}]}
8 file arch/mips/sibyte/dev/sbscd.c sbscd
10 # On-board I/O (slow I/O bridge)
11 device sbobio {[addr = -1], [intr[2] = {-1,-1}]}
12 attach sbobio at zbbus
13 file arch/mips/sibyte/dev/sbobio.c sbobio
15 # Generic bus, hang off of sbobio
16 device sbgbus {[chipsel = -1], [offset = 0], [intr[2] = {-1,-1}]}
17 attach sbgbus at sbobio
18 file arch/mips/sibyte/dev/sbgbus.c sbgbus
20 # I/O Bridge Zero attachment to ZBbus
23 file arch/mips/sibyte/pci/sbbrz.c sbbrz
24 file arch/mips/sibyte/pci/sbbrz_pci.c sbbrz
26 # Instantiated SB-1250 PCI Host bridge
29 file arch/mips/sibyte/pci/sbpcihb.c sbpcihb
31 # SB-1250 LDT Host bridge (acts like ppb)
32 device sbldthb: pcibus
34 file arch/mips/sibyte/pci/sbldthb.c sbldthb
39 attach sbtimer at sbscd
40 file arch/mips/sibyte/dev/sbtimer.c sbtimer
42 device sbwdog: sysmon_wdog
43 attach sbwdog at sbscd
44 file arch/mips/sibyte/dev/sbwdog.c sbwdog
48 # SB1250 MAC (XXX: maybe add mii_bitbang?)
49 device sbmac: arp, ether, ifnet, mii, mii_bitbang
50 attach sbmac at sbobio
51 file arch/mips/sibyte/dev/sbmac.c sbmac
53 # SB1250 built-in (asynchronous) serial ports
55 attach sbscn at sbobio
56 file arch/mips/sibyte/dev/sbscn.c sbscn needs-flag
59 # need to think about SMBus more, just hack something together
60 # temporariliy so we can use the RTC.
63 device smbus {[chan = -1], [dev = -1]}
64 attach smbus at sbobio
65 file arch/mips/sibyte/dev/sbsmbus.c smbus
68 # XXX also, this should be in sbmips/conf/files.sbmips
69 # Bogus RTC attachment
74 attach m41t81rtc at smbus
76 file arch/sbmips/sbmips/rtc.c xirtc | m41t81rtc