sys/arch/mmeye/dev/mmeyepcmciareg.h

   1 /*      $NetBSD$        */
   2
   3 /*
   4  * Copyright (c) 1997 Marc Horowitz.  All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  * 3. All advertising materials mentioning features or use of this software
  15  *    must display the following acknowledgement:
  16  *      This product includes software developed by Marc Horowitz.
  17  * 4. The name of the author may not be used to endorse or promote products
  18  *    derived from this software without specific prior written permission.
  19  *
  20  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  21  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  22  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  23  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  24  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  25  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  26  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  27  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  28  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  29  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  30  */
  31
  32
  33 #define MMEYEPCMCIA_IOSIZE              2
  34
  35 #define MMEYEPCMCIA_REG_INDEX           0
  36 #define MMEYEPCMCIA_REG_DATA            1
  37
  38 /*
  39  * The MMEYEPCMCIA allows two chips to share the same address.  In order not to run
  40  * afoul of the netbsd device model, this driver will treat those chips as
  41  * the same device.
  42  */
  43
  44 #define MMEYEPCMCIA_CHIP0_BASE          0x00
  45 #define MMEYEPCMCIA_CHIP1_BASE          0x80
  46
  47 /* Each MMEYEPCMCIA chip can drive two sockets */
  48
  49 #define MMEYEPCMCIA_SOCKETA_INDEX       0x00
  50 #define MMEYEPCMCIA_SOCKETB_INDEX       0x40
  51
  52 /* general setup registers */
  53
  54 #define MMEYEPCMCIA_IDENT                               0x00    /* RO */
  55 #define MMEYEPCMCIA_IDENT_IFTYPE_MASK                   0xC0
  56 #define MMEYEPCMCIA_IDENT_IFTYPE_IO_ONLY                0x00
  57 #define MMEYEPCMCIA_IDENT_IFTYPE_MEM_ONLY               0x40
  58 #define MMEYEPCMCIA_IDENT_IFTYPE_MEM_AND_IO             0x80
  59 #define MMEYEPCMCIA_IDENT_IFTYPE_RESERVED               0xC0
  60 #define MMEYEPCMCIA_IDENT_ZERO                          0x30
  61 #define MMEYEPCMCIA_IDENT_REV_MASK                      0x0F
  62 #define MMEYEPCMCIA_IDENT_REV_I82365SLR0                0x02
  63 #define MMEYEPCMCIA_IDENT_REV_I82365SLR1                0x03
  64
  65 #define MMEYEPCMCIA_IF_STATUS                   0x00    /* RO */
  66 #define MMEYEPCMCIA_IF_STATUS_GPI                       0x80 /* General Purpose Input */
  67 #define MMEYEPCMCIA_IF_STATUS_POWERACTIVE               0x40
  68 #define MMEYEPCMCIA_IF_STATUS_READY                     0x20 /* really READY/!BUSY */
  69 #define MMEYEPCMCIA_IF_STATUS_MEM_WP                    0x10
  70 #define MMEYEPCMCIA_IF_STATUS_CARDDETECT_MASK           0x30
  71 #define MMEYEPCMCIA_IF_STATUS_CARDDETECT_PRESENT        0x00
  72 #define MMEYEPCMCIA_IF_STATUS_BATTERY_MASK              0x03
  73 #define MMEYEPCMCIA_IF_STATUS_BATTERY_DEAD1             0x00
  74 #define MMEYEPCMCIA_IF_STATUS_BATTERY_DEAD2             0x01
  75 #define MMEYEPCMCIA_IF_STATUS_BATTERY_WARNING           0x02
  76 #define MMEYEPCMCIA_IF_STATUS_BATTERY_GOOD              0x03
  77 #define MMEYEPCMCIA_IF_STATUS_RESET                  0x08
  78 #define MMEYEPCMCIA_IF_STATUS_BUSWIDTH               0x40
  79
  80 #define MMEYEPCMCIA_PWRCTL                              0x02    /* RW */
  81 #define MMEYEPCMCIA_PWRCTL_OE                           0x80    /* output enable */
  82 #define MMEYEPCMCIA_PWRCTL_DISABLE_RESETDRV             0x40
  83 #define MMEYEPCMCIA_PWRCTL_AUTOSWITCH_ENABLE            0x20
  84 #define MMEYEPCMCIA_PWRCTL_PWR_ENABLE                   0x10
  85 #define MMEYEPCMCIA_PWRCTL_VPP2_MASK                    0x0C
  86 /* XXX these are a little unclear from the data sheet */
  87 #define MMEYEPCMCIA_PWRCTL_VPP2_RESERVED                0x0C
  88 #define MMEYEPCMCIA_PWRCTL_VPP2_EN1                     0x08
  89 #define MMEYEPCMCIA_PWRCTL_VPP2_EN0                     0x04
  90 #define MMEYEPCMCIA_PWRCTL_VPP2_ENX                     0x00
  91 #define MMEYEPCMCIA_PWRCTL_VPP1_MASK                    0x03
  92 /* XXX these are a little unclear from the data sheet */
  93 #define MMEYEPCMCIA_PWRCTL_VPP1_RESERVED                0x03
  94 #define MMEYEPCMCIA_PWRCTL_VPP1_EN1                     0x02
  95 #define MMEYEPCMCIA_PWRCTL_VPP1_EN0                     0x01
  96 #define MMEYEPCMCIA_PWRCTL_VPP1_ENX                     0x00
  97
  98 #define MMEYEPCMCIA_CSC                         0x04    /* RW */
  99 #define MMEYEPCMCIA_CSC_ZERO                            0xE0
 100 #define MMEYEPCMCIA_CSC_GPI                             0x10
 101 #define MMEYEPCMCIA_CSC_CD                              0x08 /* Card Detect Change */
 102 #define MMEYEPCMCIA_CSC_READY                           0x04
 103 #define MMEYEPCMCIA_CSC_BATTWARN                        0x02
 104 #define MMEYEPCMCIA_CSC_BATTDEAD                        0x01    /* for memory cards */
 105 #define MMEYEPCMCIA_CSC_RI                              0x01    /* for i/o cards */
 106
 107 #define MMEYEPCMCIA_ADDRWIN_ENABLE                      0x06    /* RW */
 108 #define MMEYEPCMCIA_ADDRWIN_ENABLE_IO1                  0x80
 109 #define MMEYEPCMCIA_ADDRWIN_ENABLE_IO0                  0x40
 110 #define MMEYEPCMCIA_ADDRWIN_ENABLE_MEMCS16              0x20    /* rtfds if you care */
 111 #define MMEYEPCMCIA_ADDRWIN_ENABLE_MEM4         0x10
 112 #define MMEYEPCMCIA_ADDRWIN_ENABLE_MEM3         0x08
 113 #define MMEYEPCMCIA_ADDRWIN_ENABLE_MEM2         0x04
 114 #define MMEYEPCMCIA_ADDRWIN_ENABLE_MEM1         0x02
 115 #define MMEYEPCMCIA_ADDRWIN_ENABLE_MEM0         0x01
 116
 117 #define MMEYEPCMCIA_CARD_DETECT                 0x16    /* RW */
 118 #define MMEYEPCMCIA_CARD_DETECT_RESERVED                0xC0
 119 #define MMEYEPCMCIA_CARD_DETECT_SW_INTR         0x20
 120 #define MMEYEPCMCIA_CARD_DETECT_RESUME_ENABLE           0x10
 121 #define MMEYEPCMCIA_CARD_DETECT_GPI_TRANSCTL            0x08
 122 #define MMEYEPCMCIA_CARD_DETECT_GPI_ENABLE              0x04
 123 #define MMEYEPCMCIA_CARD_DETECT_CFGRST_ENABLE           0x02
 124 #define MMEYEPCMCIA_CARD_DETECT_MEMDLY_INHIBIT          0x01
 125
 126 /* interrupt registers */
 127
 128 #define MMEYEPCMCIA_INTR                                0x03    /* RW */
 129 #define MMEYEPCMCIA_INTR_RI_ENABLE                      0x80
 130 #define MMEYEPCMCIA_INTR_RESET                          0x40    /* active low (zero) */
 131 #define MMEYEPCMCIA_INTR_CARDTYPE_MASK                  0x20
 132 #define MMEYEPCMCIA_INTR_CARDTYPE_IO                    0x20
 133 #define MMEYEPCMCIA_INTR_CARDTYPE_MEM                   0x00
 134 #define MMEYEPCMCIA_INTR_ENABLE                 0x10
 135 #define MMEYEPCMCIA_INTR_IRQ_MASK                       0x0F
 136 #define MMEYEPCMCIA_INTR_IRQ_SHIFT                      0
 137 #define MMEYEPCMCIA_INTR_IRQ_NONE                       0x00
 138 #define MMEYEPCMCIA_INTR_IRQ_RESERVED1                  0x01
 139 #define MMEYEPCMCIA_INTR_IRQ_RESERVED2                  0x02
 140 #define MMEYEPCMCIA_INTR_IRQ3                           0x03
 141 #define MMEYEPCMCIA_INTR_IRQ4                           0x04
 142 #define MMEYEPCMCIA_INTR_IRQ5                           0x05
 143 #define MMEYEPCMCIA_INTR_IRQ_RESERVED6                  0x06
 144 #define MMEYEPCMCIA_INTR_IRQ7                           0x07
 145 #define MMEYEPCMCIA_INTR_IRQ_RESERVED8                  0x08
 146 #define MMEYEPCMCIA_INTR_IRQ9                           0x09
 147 #define MMEYEPCMCIA_INTR_IRQ10                          0x0A
 148 #define MMEYEPCMCIA_INTR_IRQ11                          0x0B
 149 #define MMEYEPCMCIA_INTR_IRQ12                          0x0C
 150 #define MMEYEPCMCIA_INTR_IRQ_RESERVED13         0x0D
 151 #define MMEYEPCMCIA_INTR_IRQ14                          0x0E
 152 #define MMEYEPCMCIA_INTR_IRQ15                          0x0F
 153
 154 #define MMEYEPCMCIA_INTR_IRQ_VALIDMASK                  0xDEB8 /* 1101 1110 1011 1000 */
 155
 156 #define MMEYEPCMCIA_CSC_INTR                            0x05    /* RW */
 157 #define MMEYEPCMCIA_CSC_INTR_IRQ_MASK                   0xF0
 158 #define MMEYEPCMCIA_CSC_INTR_IRQ_SHIFT                  4
 159 #define MMEYEPCMCIA_CSC_INTR_IRQ_NONE                   0x00
 160 #define MMEYEPCMCIA_CSC_INTR_IRQ_RESERVED1              0x10
 161 #define MMEYEPCMCIA_CSC_INTR_IRQ_RESERVED2              0x20
 162 #define MMEYEPCMCIA_CSC_INTR_IRQ3                       0x30
 163 #define MMEYEPCMCIA_CSC_INTR_IRQ4                       0x40
 164 #define MMEYEPCMCIA_CSC_INTR_IRQ5                       0x50
 165 #define MMEYEPCMCIA_CSC_INTR_IRQ_RESERVED6              0x60
 166 #define MMEYEPCMCIA_CSC_INTR_IRQ7                       0x70
 167 #define MMEYEPCMCIA_CSC_INTR_IRQ_RESERVED8              0x80
 168 #define MMEYEPCMCIA_CSC_INTR_IRQ9                       0x90
 169 #define MMEYEPCMCIA_CSC_INTR_IRQ10                      0xA0
 170 #define MMEYEPCMCIA_CSC_INTR_IRQ11                      0xB0
 171 #define MMEYEPCMCIA_CSC_INTR_IRQ12                      0xC0
 172 #define MMEYEPCMCIA_CSC_INTR_IRQ_RESERVED13             0xD0
 173 #define MMEYEPCMCIA_CSC_INTR_IRQ14                      0xE0
 174 #define MMEYEPCMCIA_CSC_INTR_IRQ15                      0xF0
 175 #define MMEYEPCMCIA_CSC_INTR_CD_ENABLE                  0x08
 176 #define MMEYEPCMCIA_CSC_INTR_READY_ENABLE               0x04
 177 #define MMEYEPCMCIA_CSC_INTR_BATTWARN_ENABLE            0x02
 178 #define MMEYEPCMCIA_CSC_INTR_BATTDEAD_ENABLE            0x01    /* for memory cards */
 179 #define MMEYEPCMCIA_CSC_INTR_RI_ENABLE                  0x01    /* for I/O cards */
 180
 181 #define MMEYEPCMCIA_CSC_INTR_IRQ_VALIDMASK              0xDEB8 /* 1101 1110 1011 1000 */
 182
 183 /* I/O registers */
 184
 185 #define MMEYEPCMCIA_IO_WINS                             2
 186
 187 #define MMEYEPCMCIA_IOCTL                               0x07    /* RW */
 188 #define MMEYEPCMCIA_IOCTL_IO1_WAITSTATE         0x80
 189 #define MMEYEPCMCIA_IOCTL_IO1_ZEROWAIT                  0x40
 190 #define MMEYEPCMCIA_IOCTL_IO1_IOCS16SRC_MASK            0x20
 191 #define MMEYEPCMCIA_IOCTL_IO1_IOCS16SRC_CARD            0x20
 192 #define MMEYEPCMCIA_IOCTL_IO1_IOCS16SRC_DATASIZE        0x00
 193 #define MMEYEPCMCIA_IOCTL_IO1_DATASIZE_MASK             0x10
 194 #define MMEYEPCMCIA_IOCTL_IO1_DATASIZE_16BIT            0x10
 195 #define MMEYEPCMCIA_IOCTL_IO1_DATASIZE_8BIT             0x00
 196 #define MMEYEPCMCIA_IOCTL_IO0_WAITSTATE         0x08
 197 #define MMEYEPCMCIA_IOCTL_IO0_ZEROWAIT                  0x04
 198 #define MMEYEPCMCIA_IOCTL_IO0_IOCS16SRC_MASK            0x02
 199 #define MMEYEPCMCIA_IOCTL_IO0_IOCS16SRC_CARD            0x02
 200 #define MMEYEPCMCIA_IOCTL_IO0_IOCS16SRC_DATASIZE        0x00
 201 #define MMEYEPCMCIA_IOCTL_IO0_DATASIZE_MASK             0x01
 202 #define MMEYEPCMCIA_IOCTL_IO0_DATASIZE_16BIT            0x01
 203 #define MMEYEPCMCIA_IOCTL_IO0_DATASIZE_8BIT             0x00
 204
 205 #define MMEYEPCMCIA_IOADDR0_START_LSB                   0x08
 206 #define MMEYEPCMCIA_IOADDR0_START_MSB                   0x09
 207 #define MMEYEPCMCIA_IOADDR0_STOP_LSB                    0x0A
 208 #define MMEYEPCMCIA_IOADDR0_STOP_MSB                    0x0B
 209 #define MMEYEPCMCIA_IOADDR1_START_LSB                   0x0C
 210 #define MMEYEPCMCIA_IOADDR1_START_MSB                   0x0D
 211 #define MMEYEPCMCIA_IOADDR1_STOP_LSB                    0x0E
 212 #define MMEYEPCMCIA_IOADDR1_STOP_MSB                    0x0F
 213
 214 /* memory registers */
 215
 216 /*
 217  * memory window addresses refer to bits A23-A12 of the ISA system memory
 218  * address.  This is a shift of 12 bits.  The LSB contains A19-A12, and the
 219  * MSB contains A23-A20, plus some other bits.
 220  */
 221
 222 #define MMEYEPCMCIA_MEM_WINS                            5
 223
 224 #define MMEYEPCMCIA_MEM_SHIFT                           12
 225 #define MMEYEPCMCIA_MEM_PAGESIZE                        (1<<MMEYEPCMCIA_MEM_SHIFT)
 226
 227 #define MMEYEPCMCIA_SYSMEM_ADDRX_SHIFT                          MMEYEPCMCIA_MEM_SHIFT
 228 #define MMEYEPCMCIA_SYSMEM_ADDRX_START_MSB_DATASIZE_MASK        0x80
 229 #define MMEYEPCMCIA_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT       0x80
 230 #define MMEYEPCMCIA_SYSMEM_ADDRX_START_MSB_DATASIZE_8BIT        0x00
 231 #define MMEYEPCMCIA_SYSMEM_ADDRX_START_MSB_ZEROWAIT             0x40
 232 #define MMEYEPCMCIA_SYSMEM_ADDRX_START_MSB_SCRATCH_MASK 0x30
 233 #define MMEYEPCMCIA_SYSMEM_ADDRX_START_MSB_ADDR_MASK            0x0F
 234
 235 #define MMEYEPCMCIA_SYSMEM_ADDRX_STOP_MSB_WAIT_MASK             0xC0
 236 #define MMEYEPCMCIA_SYSMEM_ADDRX_STOP_MSB_WAIT0         0x00
 237 #define MMEYEPCMCIA_SYSMEM_ADDRX_STOP_MSB_WAIT1         0x40
 238 #define MMEYEPCMCIA_SYSMEM_ADDRX_STOP_MSB_WAIT2         0x80
 239 #define MMEYEPCMCIA_SYSMEM_ADDRX_STOP_MSB_WAIT3         0xC0
 240 #define MMEYEPCMCIA_SYSMEM_ADDRX_STOP_MSB_ADDR_MASK             0x0F
 241
 242 /*
 243  * The card side of a memory mapping consists of bits A19-A12 of the card
 244  * memory address in the LSB, and A25-A20 plus some other bits in the MSB.
 245  * Again, the shift is 12 bits.
 246  */
 247
 248 #define MMEYEPCMCIA_CARDMEM_ADDRX_SHIFT         MMEYEPCMCIA_MEM_SHIFT
 249 #define MMEYEPCMCIA_CARDMEM_ADDRX_MSB_WP                0x80
 250 #define MMEYEPCMCIA_CARDMEM_ADDRX_MSB_REGACTIVE_MASK    0x40
 251 #define MMEYEPCMCIA_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR    0x40
 252 #define MMEYEPCMCIA_CARDMEM_ADDRX_MSB_REGACTIVE_COMMON  0x00
 253 #define MMEYEPCMCIA_CARDMEM_ADDRX_MSB_ADDR_MASK 0x3F
 254
 255 #define MMEYEPCMCIA_SYSMEM_ADDR0_START_LSB              0x10
 256 #define MMEYEPCMCIA_SYSMEM_ADDR0_START_MSB              0x11
 257 #define MMEYEPCMCIA_SYSMEM_ADDR0_STOP_LSB               0x12
 258 #define MMEYEPCMCIA_SYSMEM_ADDR0_STOP_MSB               0x13
 259
 260 #define MMEYEPCMCIA_CARDMEM_ADDR0_LSB                   0x14
 261 #define MMEYEPCMCIA_CARDMEM_ADDR0_MSB                   0x15
 262
 263 /* #define      MMEYEPCMCIA_RESERVED                    0x17 */
 264
 265 #define MMEYEPCMCIA_SYSMEM_ADDR1_START_LSB              0x18
 266 #define MMEYEPCMCIA_SYSMEM_ADDR1_START_MSB              0x19
 267 #define MMEYEPCMCIA_SYSMEM_ADDR1_STOP_LSB               0x1A
 268 #define MMEYEPCMCIA_SYSMEM_ADDR1_STOP_MSB               0x1B
 269
 270 #define MMEYEPCMCIA_CARDMEM_ADDR1_LSB                   0x1C
 271 #define MMEYEPCMCIA_CARDMEM_ADDR1_MSB                   0x1D
 272
 273 #define MMEYEPCMCIA_SYSMEM_ADDR2_START_LSB              0x20
 274 #define MMEYEPCMCIA_SYSMEM_ADDR2_START_MSB              0x21
 275 #define MMEYEPCMCIA_SYSMEM_ADDR2_STOP_LSB               0x22
 276 #define MMEYEPCMCIA_SYSMEM_ADDR2_STOP_MSB               0x23
 277
 278 #define MMEYEPCMCIA_CARDMEM_ADDR2_LSB                   0x24
 279 #define MMEYEPCMCIA_CARDMEM_ADDR2_MSB                   0x25
 280
 281 /* #define      MMEYEPCMCIA_RESERVED                    0x26 */
 282 /* #define      MMEYEPCMCIA_RESERVED                    0x27 */
 283
 284 #define MMEYEPCMCIA_SYSMEM_ADDR3_START_LSB              0x28
 285 #define MMEYEPCMCIA_SYSMEM_ADDR3_START_MSB              0x29
 286 #define MMEYEPCMCIA_SYSMEM_ADDR3_STOP_LSB               0x2A
 287 #define MMEYEPCMCIA_SYSMEM_ADDR3_STOP_MSB               0x2B
 288
 289 #define MMEYEPCMCIA_CARDMEM_ADDR3_LSB                   0x2C
 290 #define MMEYEPCMCIA_CARDMEM_ADDR3_MSB                   0x2D
 291
 292 /* #define      MMEYEPCMCIA_RESERVED                    0x2E */
 293 /* #define      MMEYEPCMCIA_RESERVED                    0x2F */
 294
 295 #define MMEYEPCMCIA_SYSMEM_ADDR4_START_LSB              0x30
 296 #define MMEYEPCMCIA_SYSMEM_ADDR4_START_MSB              0x31
 297 #define MMEYEPCMCIA_SYSMEM_ADDR4_STOP_LSB               0x32
 298 #define MMEYEPCMCIA_SYSMEM_ADDR4_STOP_MSB               0x33
 299
 300 #define MMEYEPCMCIA_CARDMEM_ADDR4_LSB                   0x34
 301 #define MMEYEPCMCIA_CARDMEM_ADDR4_MSB                   0x35
 302
 303 /* #define      MMEYEPCMCIA_RESERVED                    0x36 */
 304 /* #define      MMEYEPCMCIA_RESERVED                    0x37 */
 305 /* #define      MMEYEPCMCIA_RESERVED                    0x38 */
 306 /* #define      MMEYEPCMCIA_RESERVED                    0x39 */
 307 /* #define      MMEYEPCMCIA_RESERVED                    0x3A */
 308 /* #define      MMEYEPCMCIA_RESERVED                    0x3B */
 309 /* #define      MMEYEPCMCIA_RESERVED                    0x3C */
 310 /* #define      MMEYEPCMCIA_RESERVED                    0x3D */
 311 /* #define      MMEYEPCMCIA_RESERVED                    0x3E */
 312 /* #define      MMEYEPCMCIA_RESERVED                    0x3F */
 313
 314 /* vendor-specific registers */
 315
 316 #define MMEYEPCMCIA_INTEL_GLOBAL_CTL                    0x1E    /* RW */
 317 #define MMEYEPCMCIA_INTEL_GLOBAL_CTL_RESERVED           0xF0
 318 #define MMEYEPCMCIA_INTEL_GLOBAL_CTL_IRQ14PULSE_ENABLE  0x08
 319 #define MMEYEPCMCIA_INTEL_GLOBAL_CTL_EXPLICIT_CSC_ACK   0x04
 320 #define MMEYEPCMCIA_INTEL_GLOBAL_CTL_IRQLEVEL_ENABLE    0x02
 321 #define MMEYEPCMCIA_INTEL_GLOBAL_CTL_POWERDOWN          0x01
 322
 323 #define MMEYEPCMCIA_CIRRUS_MISC_CTL_2                   0x1E
 324 #define MMEYEPCMCIA_CIRRUS_MISC_CTL_2_SUSPEND           0x04
 325
 326 #define MMEYEPCMCIA_CIRRUS_CHIP_INFO                    0x1F
 327 #define MMEYEPCMCIA_CIRRUS_CHIP_INFO_CHIP_ID            0xC0
 328 #define MMEYEPCMCIA_CIRRUS_CHIP_INFO_SLOTS              0x20
 329 #define MMEYEPCMCIA_CIRRUS_CHIP_INFO_REV                0x1F
 330
 331 /* Brains MMTA attribute memory space size */
 332 #define MMEYEPCMCIA_ATTRMEM_SIZE 0x2000000