sys/arch/news68k/dev/dmac_0266.h

   1 /*      $NetBSD: dmac_0266.h,v 1.5 2008/05/07 13:02:00 tsutsui Exp $    */
   2
   3 /*-
   4  * Copyright (c) 1999 Izumi Tsutsui.  All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  *
  15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  16  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  17  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  18  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  19  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  20  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  21  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  22  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  23  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  24  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  25  */
  26
  27 /* DMAC 266 register definition */
  28
  29 struct dma_regs {
  30         volatile uint32_t ctl;                  /* Control Register     */
  31 #define  DC_CTL_RST     0x04                    /* Soft Reset           */
  32 #define  DC_CTL_MOD     0x02                    /* set transfer dir     */
  33 #define  DC_CTL_ENB     0x01                    /* set Enable           */
  34
  35         volatile uint32_t stat;                 /* Status Register      */
  36 #define  DC_ST_TCZ      0x10                    /* Transfer Count Zero  */
  37 #define  DC_ST_INT      0x08                    /* Interrupt            */
  38 #define  DC_ST_MOD      0x02                    /* monitor transfer dir */
  39 #define  DC_ST_ENB      0x01                    /* monitor Enable       */
  40
  41         volatile uint32_t tcnt;                 /* transfer counter     */
  42         volatile uint32_t tag;                  /* Tag Register         */
  43         volatile uint32_t offset;               /* Offset Register      */
  44         volatile uint32_t mapent;               /* Map entry Register   */
  45 };
  46
  47 #define DMAC_WAIT       __asm volatile ("nop; nop; nop; nop; nop; nop")
  48
  49 #define DMAC_SEG_SIZE   0x1000 /* 4kbyte per DMA segment */
  50 #define DMAC_SEG_OFFSET 0x0fff
  51 #define DMAC_SEG_SHIFT  12