sys/arch/newsmips/apbus/spifireg.h

   1 /*      $NetBSD: spifireg.h,v 1.1 2000/10/30 10:07:35 tsubai Exp $      */
   2
   3 /*-
   4  * Copyright (c) 2000 Tsubai Masanari.  All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  * 3. The name of the author may not be used to endorse or promote products
  15  *    derived from this software without specific prior written permission.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  18  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  19  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  20  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  21  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 struct spifi_reg {
  30         volatile uint32_t spstat;       /* RO: SPIFI state              */
  31         volatile uint32_t cmlen;        /* RW: Command/message length   */
  32         volatile uint32_t cmdpage;      /* RW: Command page             */
  33         volatile uint32_t count_hi;     /* RW: Data count (high)        */
  34         volatile uint32_t count_mid;    /* RW:            (mid)         */
  35         volatile uint32_t count_low;    /* RW:            (low)         */
  36         volatile uint32_t svptr_hi;     /* RO: Saved data pointer (high)*/
  37         volatile uint32_t svptr_mid;    /* RO:                    (mid) */
  38         volatile uint32_t svptr_low;    /* RO:                    (low) */
  39         volatile uint32_t intr;         /* RW: Processor interrupt      */
  40         volatile uint32_t imask;        /* RW: Processor interrupt mask */
  41         volatile uint32_t prctrl;       /* RW: Processor control        */
  42         volatile uint32_t prstat;       /* RO: Processor status         */
  43         volatile uint32_t init_status;  /* RO: Initiator status         */
  44         volatile uint32_t fifoctrl;     /* RW: FIFO control             */
  45         volatile uint32_t fifodata;     /* RW: FIFO data                */
  46         volatile uint32_t config;       /* RW: Configuration            */
  47         volatile uint32_t data_xfer;    /* RW: Data transfer            */
  48         volatile uint32_t autocmd;      /* RW: Auto command control     */
  49         volatile uint32_t autostat;     /* RW: Auto status control      */
  50         volatile uint32_t resel;        /* RW: Reselection              */
  51         volatile uint32_t select;       /* RW: Selection                */
  52         volatile uint32_t prcmd;        /* WO: Processor command        */
  53         volatile uint32_t auxctrl;      /* RW: Aux control              */
  54         volatile uint32_t autodata;     /* RW: Auto data control        */
  55         volatile uint32_t loopctrl;     /* RW: Loopback control         */
  56         volatile uint32_t loopdata;     /* RW: Loopback data            */
  57         volatile uint32_t identify;     /* WO: Identify (?)             */
  58         volatile uint32_t complete;     /* WO: Command complete (?)     */
  59         volatile uint32_t scsi_status;  /* WO: SCSI status (?)          */
  60         volatile uint32_t data;         /* RW: Data register (?)        */
  61         volatile uint32_t icond;        /* RO: Interrupt condition      */
  62         volatile uint32_t fastwide;     /* RW: Fast/wide enable         */
  63         volatile uint32_t exctrl;       /* RW: Extended control         */
  64         volatile uint32_t exstat;       /* RW: Extended status          */
  65         volatile uint32_t test;         /* RW: SPIFI test register      */
  66         volatile uint32_t quematch;     /* RW: Queue match              */
  67         volatile uint32_t quecode;      /* RW: Queue code               */
  68         volatile uint32_t quetag;       /* RW: Queue tag                */
  69         volatile uint32_t quepage;      /* RW: Queue page               */
  70         uint32_t image[88];             /* (image of the above)         */
  71         struct {
  72                 volatile uint32_t cdb[12]; /* RW: Command descriptor block */
  73                 volatile uint32_t quecode; /* RW: Queue code            */
  74                 volatile uint32_t quetag;  /* RW: Queue tag             */
  75                 volatile uint32_t idmsg;   /* RW: Identify message      */
  76                 volatile uint32_t status;  /* RW: SCSI status           */
  77         } cmbuf[8];
  78 };
  79
  80 /* spstat */
  81 #define SPS_IDLE        0x00
  82 #define SPS_SEL         0x01
  83 #define SPS_ARB         0x02
  84 #define SPS_RESEL       0x03
  85 #define SPS_MSGOUT      0x04
  86 #define SPS_COMMAND     0x05
  87 #define SPS_DISCON      0x06
  88 #define SPS_NXIN        0x07
  89 #define SPS_INTR        0x08
  90 #define SPS_NXOUT       0x09
  91 #define SPS_CCOMP       0x0a
  92 #define SPS_SVPTR       0x0b
  93 #define SPS_STATUS      0x0c
  94 #define SPS_MSGIN       0x0d
  95 #define SPS_DATAOUT     0x0e
  96 #define SPS_DATAIN      0x0f
  97
  98 /* cmlen */
  99 #define CML_LENMASK     0x0f
 100 #define CML_AMSG_EN     0x40
 101 #define CML_ACOM_EN     0x80
 102
 103 /* intr and imask */
 104 #define INTR_BSRQ       0x01
 105 #define INTR_COMRECV    0x02
 106 #define INTR_PERR       0x04
 107 #define INTR_TIMEO      0x08
 108 #define INTR_DERR       0x10
 109 #define INTR_TGSEL      0x20
 110 #define INTR_DISCON     0x40
 111 #define INTR_FCOMP      0x80
 112
 113 #define INTR_BITMASK \
 114     "\20\10FCOMP\07DISCON\06TGSEL\05DERR\04TIMEO\03PERR\02COMRECV\01BSRQ"
 115
 116 /* prstat */
 117 #define PRS_IO          0x08
 118 #define PRS_CD          0x10
 119 #define PRS_MSG         0x20
 120 #define PRS_ATN         0x40
 121 #define PRS_Z           0x80
 122 #define PRS_PHASE       (PRS_MSG | PRS_CD | PRS_IO)
 123
 124 #define PRS_BITMASK "\20\10Z\07ATN\06MSG\05CD\04IO"
 125
 126 /* init_status */
 127 #define IST_ACK         0x40
 128
 129 /* fifoctrl */
 130 #define FIFOC_FSLOT     0x0f    /* Free slots in FIFO */
 131 #define FIFOC_SSTKACT   0x10    /* Synchronous stack active (?) */
 132 #define FIFOC_RQOVRN    0x20
 133 #define FIFOC_CLREVEN   0x00
 134 #define FIFOC_CLRODD    0x40
 135 #define FIFOC_FLUSH     0x80
 136 #define FIFOC_LOAD      0xc0
 137
 138 /* config */
 139 #define CONFIG_PGENEN   0x08    /* Parity generation enable */
 140 #define CONFIG_PCHKEN   0x10    /* Parity checking enable */
 141 #define CONFIG_WORDEN   0x20
 142 #define CONFIG_AUTOID   0x40
 143 #define CONFIG_DMABURST 0x80
 144
 145 /* select */
 146 #define SEL_SETATN      0x02
 147 #define SEL_IRESELEN    0x04
 148 #define SEL_ISTART      0x08
 149 #define SEL_WATN        0x80
 150
 151 /* prcmd */
 152 #define PRC_DATAOUT     0
 153 #define PRC_DATAIN      1
 154 #define PRC_COMMAND     2
 155 #define PRC_STATUS      3
 156 #define PRC_TRPAD       4
 157 #define PRC_MSGOUT      6
 158 #define PRC_MSGIN       7
 159 #define PRC_KILLREQ     0x08
 160 #define PRC_CLRACK      0x10
 161 #define PRC_NJMP        0x80
 162
 163 /* auxctrl */
 164 #define AUXCTRL_DMAEDGE 0x04
 165 #define AUXCTRL_SETRST  0x20    /* Bus reset (?) */
 166 #define AUXCTRL_CRST    0x40
 167 #define AUXCTRL_SRST    0x80
 168
 169 /* autodata */
 170 #define ADATA_IN        0x40
 171 #define ADATA_EN        0x80
 172
 173 /* icond */
 174 #define ICOND_ADATAOFF  0x02
 175 #define ICOND_AMSGOFF   0x06
 176 #define ICOND_ACMDOFF   0x0a
 177 #define ICOND_ASTATOFF  0x0e
 178 #define ICOND_SVPTEXP   0x10
 179 #define ICOND_ADATAMIS  0x20
 180 #define ICOND_CNTZERO   0x40
 181 #define ICOND_UXPHASEZ  0x80
 182 #define ICOND_UXPHASENZ 0x81
 183 #define ICOND_NXTREQ    0xa0
 184 #define ICOND_UKMSGZ    0xc0
 185 #define ICOND_UKMSGNZ   0xc1
 186 #define ICOND_UBF       0xe0    /* Unexpected bus free */
 187
 188 /* fastwide */
 189 #define FAST_FASTEN     0x01
 190
 191 /* exctrl */
 192 #define EXC_IPLOCK      0x04    /* Initiator page lock */
 193
 194 /* exstat */
 195 #define EXS_UBF         0x08    /* Unexpected bus free */