sys/arch/next68k/dev/clockreg.h

   1 /*      $NetBSD: clockreg.h,v 1.1.1.1 1998/06/09 07:53:05 dbj Exp $        */
   2 /*
   3  * Copyright (c) 1997 Rolf Grossmann
   4  * All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  * 3. All advertising materials mentioning features or use of this software
  15  *    must display the following acknowledgement:
  16  *      This product includes software developed by Rolf Grossmann.
  17  * 4. The name of the author may not be used to endorse or promote products
  18  *    derived from this software without specific prior written permission
  19  *
  20  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  21  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  22  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  23  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  24  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  25  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  26  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  27  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  28  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  29  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  30  */
  31
  32 /*
  33  * NeXT clock registers
  34  */
  35
  36 struct scr2 {                           /* zeroed at power-on, read/write */
  37     u_int s_dsp_reset : 1,
  38         s_dsp_block_end : 1,
  39         s_dsp_unpacked : 1,
  40         s_dsp_mode_B : 1,
  41         s_dsp_mode_A : 1,
  42         s_remote_int : 1,
  43         s_local_int : 2,        /* in fact :1 reserved and :1 local_int? */
  44         s_dram_256K : 4,
  45         s_dram_1M : 4,
  46         s_timer_on_ipl7 : 1,
  47         s_rom_wait_states : 3,
  48         s_rom_1M : 1,
  49         s_rtdata : 1,
  50         s_rtclk : 1,
  51         s_rtce : 1,
  52         s_rom_overlay : 1,
  53         s_dsp_int_en : 1,
  54         s_dsp_mem_en : 1,
  55         s_reserved : 4,
  56         s_led : 1;
  57 };
  58
  59 #define SCR2_DSP_RESET          0x80000000
  60 #define SCR2_DSP_BLOCK_END      0x40000000
  61 #define SCR2_DSP_UNPACKED       0x20000000
  62 #define SCR2_DSP_MODE_B         0x10000000
  63 #define SCR2_DSP_MODE_A         0x08000000
  64 #define SCR2_REMOTE_INT         0x04000000
  65 #define SCR2_LOCAL_INT          0x01000000
  66 #define SCR2_DRAM_256K          0x00100000
  67 #define SCR2_DRAM_1M            0x00010000
  68 #define SCR2_TIMER_ON_IPL7      0x00008000
  69 #define SCR2_ROM_WAITSTATES     0x00007000
  70 #define SCR2_ROM_1M             0x00000800
  71 #define SCR2_RTDATA             0x00000400
  72 #define SCR2_RTCLK              0x00000200
  73 #define SCR2_RTCE               0x00000100
  74 #define SCR2_ROM_OVERLAY        0x00000080
  75 #define SCR2_DSP_IE             0x00000040
  76 #define SCR2_MEM_EN             0x00000020
  77 #define SCR2_LED                0x00000001
  78
  79 /* real time clock -- old is MC68HC68T1 chip, new is MCS1850 chip */
  80 #define RTC_RAM         0x00            /* both */
  81 #define RTC_SEC         0x20            /* old BCD coded date*/
  82 #define RTC_MIN         0x21
  83 #define RTC_HRS         0x22
  84 #define RTC_DAY         0x23
  85 #define RTC_DATE        0x24
  86 #define RTC_MON         0x25
  87 #define RTC_YR          0x26
  88 #define RTC_ALARM_SEC   0x28
  89 #define RTC_ALARM_MIN   0x29
  90 #define RTC_ALARM_HR    0x2a
  91
  92 #define RTC_CNTR0       0x20            /* new */
  93 #define RTC_CNTR1       0x21
  94 #define RTC_CNTR2       0x22
  95 #define RTC_CNTR3       0x23
  96 #define RTC_ALARM0      0x24
  97 #define RTC_ALARM1      0x25
  98 #define RTC_ALARM2      0x26
  99 #define RTC_ALARM3      0x27
 100
 101 #define RTC_STATUS      0x30            /* both */
 102 #define RTC_CONTROL     0x31            /* both */
 103 #define RTC_INTRCTL     0x32            /* old */
 104
 105 /* bits in RTC_STATUS */
 106 #define RTC_NEW_CLOCK   0x80    /* new: set in new clock chip */
 107 #define RTC_FTU         0x10    /* both: set when powered up but uninitialized */
 108 #define RTC_INTR        0x08    /* new: interrupt asserted */
 109 #define RTC_LOW_BATT    0x04    /* new: low battery */
 110 #define RTC_ALARM       0x02    /* new: alarm interrupt */
 111 #define RTC_RPD         0x01    /* new: request to power down */
 112
 113 /* bits in RTC_CONTROL */
 114 #define RTC_START       0x80    /* both: start counters */
 115 #define RTC_STOP        0x00    /* both: stop counters */
 116 #define RTC_XTAL        0x30    /* old: xtal: line = 0, sel0 = sel1 = 1 */
 117 #define RTC_AUTO_PON    0x20    /* new: auto poweron after power fail */
 118 #define RTC_AE          0x10    /* new: alarm enable */
 119 #define RTC_AC          0x08    /* new: alarm clear */
 120 #define RTC_FTUC        0x04    /* new: first time up clear */
 121 #define RTC_LBE         0x02    /* new: low battery enable */
 122 #define RTC_RPDC        0x01    /* new: request to power down clear */
 123
 124 /* bits in RTC_INTRCTL */
 125 #define RTC_PDOWN       0x40    /* both: power down, bit in RTC_CONTROL on new chip */
 126 #define RTC_64HZ        0x06    /* old: periodic select = 64 Hz */
 127 #define RTC_128HZ       0x05    /* old: periodic select = 128 Hz */
 128 #define RTC_512HZ       0x03    /* old: periodic select = 512 Hz */
 129
 130 /* RTC address byte format */
 131 #define RTC_WRITE       0x80
 132 #define RTC_ADRS        0x3f
 133
 134
 135 struct timer_reg {
 136   u_char msb;
 137   u_char lsb;
 138   u_char pad0;
 139   u_char pad1;
 140   u_char csr;
 141 };
 142
 143 /* timer register */
 144 #define TIMER_REG_ENABLE        0x80
 145 #define TIMER_REG_UPDATE        0x40
 146 #define TIMER_REG_MAX           0xffff          /* Maximum value of timer */