sys/arch/powerpc/ibm4xx/dev/gpiicreg.h

   1 /*      $NetBSD: gpiicreg.h,v 1.1.4.3 2004/09/21 13:20:35 skrll Exp $   */
   2 /*      Original Tag: iicreg.h,v 1.3 2003/09/23 14:56:08 shige Exp      */
   3
   4 /*
   5  * Copyright 2001 Wasabi Systems, Inc.
   6  * All rights reserved.
   7  *
   8  * Written by Simon Burge and Eduardo Horvath for Wasabi Systems, Inc.
   9  *
  10  * Redistribution and use in source and binary forms, with or without
  11  * modification, are permitted provided that the following conditions
  12  * are met:
  13  * 1. Redistributions of source code must retain the above copyright
  14  *    notice, this list of conditions and the following disclaimer.
  15  * 2. Redistributions in binary form must reproduce the above copyright
  16  *    notice, this list of conditions and the following disclaimer in the
  17  *    documentation and/or other materials provided with the distribution.
  18  * 3. All advertising materials mentioning features or use of this software
  19  *    must display the following acknowledgement:
  20  *      This product includes software developed for the NetBSD Project by
  21  *      Wasabi Systems, Inc.
  22  * 4. The name of Wasabi Systems, Inc. may not be used to endorse
  23  *    or promote products derived from this software without specific prior
  24  *    written permission.
  25  *
  26  * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
  27  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  28  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  29  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
  30  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  31  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  32  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  33  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  34  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  35  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  36  * POSSIBILITY OF SUCH DAMAGE.
  37  */
  38
  39 #ifndef _IBM4XX_GPIICREG_H_
  40 #define _IBM4XX_GPIICREG_H_
  41
  42 /* IIC FIFO buffer size */
  43 #define IIC_FIFO_BUFSIZE        (4)
  44
  45 /*
  46  * definitions for IIC Addressing Mode
  47  */
  48 #define IIC_LADR_SHFT           1       /* LowAddr (7-bit addressing) shift */
  49 #define IIC_HADR_SHFT           1       /* HighAddr (10-bit addressing) shift */
  50
  51 /*
  52  * definitions for IIC Registers
  53  */
  54 #define IIC_MDBUF               0x00    /* Master Data Buffer */
  55 #define IIC_SDBUF               0x02    /* Slave Data Buffer */
  56 #define IIC_LMADR               0x04    /* Low Master Address */
  57 #define IIC_HMADR               0x05    /* High Master Address */
  58 #define IIC_CNTL                0x06    /* Control */
  59 #define IIC_MDCNTL              0x07    /* Mode Control */
  60 #define IIC_STS                 0x08    /* Status */
  61 #define IIC_EXTSTS              0x09    /* Extended Status */
  62 #define IIC_LSADR               0x0a    /* Low Slave Address */
  63 #define IIC_HSADR               0x0b    /* High Slave Address */
  64 #define IIC_CLKDIV              0x0c    /* Clock Divide */
  65 #define IIC_INTRMSK             0x0d    /* Interrupt Mask */
  66 #define IIC_XFRCNT              0x0e    /* Transfer Count */
  67 #define IIC_XTCNTLSS            0x0f    /* Extended Control and Slave Status */
  68 #define IIC_DIRECTCNTL          0x10    /* Direct Control */
  69 #define IIC_NREG                0x20
  70
  71 /*
  72  * Bit definitions for IIC_CNTL
  73  */
  74 #define IIC_CNTL_PT             (1u << 0)       /* Pending Transfer */
  75 #define IIC_CNTL_RW             (1u << 1)       /* Read/Write */
  76 #define IIC_CNTL_CHT            (1u << 2)       /* Chain Transfer */
  77 #define IIC_CNTL_RPST           (1u << 3)       /* Repeated Start */
  78 #define IIC_CNTL_TCT            (3u << 4)       /* Transfer Count */
  79 #define IIC_CNTL_AMD            (1u << 6)       /* Addressing Mode */
  80 #define IIC_CNTL_HMT            (1u << 7)       /* Halt Master Transfer */
  81 #define IIC_CNTL_TCT_SHFT       4
  82
  83 /*
  84  * Bit definitions for IIC_MDCNTL
  85  */
  86 #define IIC_MDCNTL_HSCL         (1u << 0)       /* Hold IIC Serial Clock Low */
  87 #define IIC_MDCNTL_EUBS         (1u << 1)       /* Exit Unknown IIC Bus State */
  88 #define IIC_MDCNTL_EINT         (1u << 2)       /* Enable Interrupt */
  89 #define IIC_MDCNTL_ESM          (1u << 3)       /* Enable Slave Mode */
  90 #define IIC_MDCNTL_FSM          (1u << 4)       /* Fast/Standard Mode */
  91 #define IIC_MDCNTL_FMDB         (1u << 6)       /* Flush Master Data Buffer */
  92 #define IIC_MDCNTL_FSDB         (1u << 7)       /* Flush Slave Data Buffer */
  93
  94 /*
  95  * Bit definitions for IIC_STS
  96  */
  97 #define IIC_STS_PT              (1u << 0)       /* RO:Pending Transfer */
  98 #define IIC_STS_IRQA            (1u << 1)       /* IRQ Active */
  99 #define IIC_STS_ERR             (1u << 2)       /* RO:Error */
 100 #define IIC_STS_SCMP            (1u << 3)       /* Stop Complete */
 101 #define IIC_STS_MDBF            (1u << 4)       /* RO:MasterDataBuffer Full */
 102 #define IIC_STS_MDBS            (1u << 5)       /* RO:MasterDataBuffer Status */
 103 #define IIC_STS_SLPR            (1u << 6)       /* Sleep Request */
 104 #define IIC_STS_SSS             (1u << 7)       /* Slave Status Set */
 105
 106 /*
 107  * Bit definitions for IIC_EXTSTS
 108  */
 109 #define IIC_EXTSTS_XFRA         (1u << 0)       /* Transfer Aborted */
 110 #define IIC_EXTSTS_ICT          (1u << 1)       /* Incomplete Transfer */
 111 #define IIC_EXTSTS_LA           (1u << 2)       /* Lost Arbitration */
 112 #define IIC_EXTSTS_IRQD         (1u << 3)       /* IRQ On-Deck */
 113 #define IIC_EXTSTS_BCS          (7u << 4)       /* RO:Bus Control State */
 114 #define IIC_EXTSTS_IRQP         (1u << 7)       /* IRQ Pending */
 115
 116 #define IIC_EXTSTS_BCS_FREE     (4u << 4)       /* BCS: Free Bus */
 117
 118 /*
 119  * Bit definitions for IIC_XFRCNT
 120  */
 121 #define IIC_INTRMSK_EIMTC       (1u << 0)       /* Enable IRQ on Reqested MT */
 122 #define IIC_INTRMSK_EITA        (1u << 1)       /* Enable IRQ on Trans Abort */
 123 #define IIC_INTRMSK_EIIC        (1u << 2)       /* Enable IRQ on Incomp*/
 124 #define IIC_INTRMSK_EIHE        (1u << 3)       /* */
 125 #define IIC_INTRMSK_EIWS        (1u << 4)       /* */
 126 #define IIC_INTRMSK_EIWC        (1u << 5)       /* */
 127 #define IIC_INTRMSK_EIRS        (1u << 6)       /* */
 128 #define IIC_INTRMSK_EIRC        (1u << 7)       /* */
 129
 130 /*
 131  * Bit definitions for IIC_XFRCNT
 132  */
 133 #define IIC_XFRCNT_STC          (7u << 4)       /* Slave Transfer Count */
 134 #define IIC_XFRCNT_MTC          (7u << 0)       /* Master Transfer Count */
 135 #define IIC_XFRCNT_STC_SHFT     4
 136
 137 /*
 138  * Bit definitions for IIC_XTCNTLSS
 139  */
 140 #define IIC_XTCNTLSS_SRST       (1u << 0)       /* Soft reset */
 141 #define IIC_XTCNTLSS_EPI        (1u << 1)       /* Enable pulsed IRQ */
 142 #define IIC_XTCNTLSS_SDBF       (1u << 2)       /* Slave data buffer full */
 143 #define IIC_XTCNTLSS_SDBD       (1u << 3)       /* Slave data buffer has data */
 144 #define IIC_XTCNTLSS_SWS        (1u << 4)       /* Slave write needs service */
 145 #define IIC_XTCNTLSS_SWC        (1u << 5)       /* Slave write complete */
 146 #define IIC_XTCNTLSS_SRS        (1u << 6)       /* Slave read needs service */
 147 #define IIC_XTCNTLSS_SRC        (1u << 7)       /* Slave read complete */
 148
 149 /*
 150  * Bit definitions for IIC_DIRECTCNTL
 151  */
 152 #define IIC_DIRECTCNTL_MSC      (1u << 0)       /* Monitor IIC Clock Line (ro)*/
 153 #define IIC_DIRECTCNTL_MSDA     (1u << 1)       /* Monitor IIC Data Line (ro) */
 154 #define IIC_DIRECTCNTL_SCC      (1u << 2)       /* IIC Clock Control */
 155 #define IIC_DIRECTCNTL_SDAC     (1u << 3)       /* IIC Data Control */
 156
 157 /*
 158  * Value definitions for IIC_CLKDIV
 159  */
 160 #define IIC_CLKDIV_20MHZ        (0x01)          /* OPB f = 20 MHz */
 161 #define IIC_CLKDIV_30MHZ        (0x02)          /* OPB 20 < f <= 30 MHz */
 162 #define IIC_CLKDIV_40MHZ        (0x03)          /* OPB 30 < f <= 40 MHz */
 163 #define IIC_CLKDIV_50MHZ        (0x04)          /* OPB 40 < f <= 50 MHz */
 164 #define IIC_CLKDIV_60MHZ        (0x05)          /* OPB 50 < f <= 60 MHz */
 165 #define IIC_CLKDIV_70MHZ        (0x06)          /* OPB 60 < f <= 70 MHz */
 166
 167 #endif  /* _IBM4XX_GPIICREG_H_ */