sys/arch/powerpc/ibm4xx/dev/ibm405gp.c

   1 /*      $NetBSD: ibm405gp.c,v 1.1.8.3 2004/09/21 13:20:35 skrll Exp $   */
   2
   3 /*
   4  * Copyright 2001 Wasabi Systems, Inc.
   5  * All rights reserved.
   6  *
   7  * Written by Eduardo Horvath and Simon Burge for Wasabi Systems, Inc.
   8  *
   9  * Redistribution and use in source and binary forms, with or without
  10  * modification, are permitted provided that the following conditions
  11  * are met:
  12  * 1. Redistributions of source code must retain the above copyright
  13  *    notice, this list of conditions and the following disclaimer.
  14  * 2. Redistributions in binary form must reproduce the above copyright
  15  *    notice, this list of conditions and the following disclaimer in the
  16  *    documentation and/or other materials provided with the distribution.
  17  * 3. All advertising materials mentioning features or use of this software
  18  *    must display the following acknowledgement:
  19  *      This product includes software developed for the NetBSD Project by
  20  *      Wasabi Systems, Inc.
  21  * 4. The name of Wasabi Systems, Inc. may not be used to endorse
  22  *    or promote products derived from this software without specific prior
  23  *    written permission.
  24  *
  25  * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
  26  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  27  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  28  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
  29  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  30  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  31  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  32  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  33  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  34  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  35  * POSSIBILITY OF SUCH DAMAGE.
  36  */
  37
  38 #include <sys/cdefs.h>
  39 __KERNEL_RCSID(0, "$NetBSD: ibm405gp.c,v 1.1.8.3 2004/09/21 13:20:35 skrll Exp $");
  40
  41 #include <sys/param.h>
  42 #include <sys/device.h>
  43 #include <sys/systm.h>
  44 #include <sys/extent.h>
  45
  46 #include <machine/bus.h>
  47 #include <dev/pci/pcivar.h>
  48
  49 #include <powerpc/ibm4xx/ibm405gp.h>
  50 #include <powerpc/ibm4xx/dev/pcicreg.h>
  51
  52 static struct powerpc_bus_space pcicfg_tag = {
  53         _BUS_SPACE_LITTLE_ENDIAN|_BUS_SPACE_MEM_TYPE,
  54         IBM405GP_PCIL0_BASE, 0x0, 0x40
  55 };
  56 static char ex_storage[EXTENT_FIXED_STORAGE_SIZE(1)]
  57     __attribute__((aligned(8)));
  58 static bus_space_tag_t pcicfg_iot = &pcicfg_tag;
  59 static bus_space_handle_t pcicfg_ioh = 0;
  60
  61 #define PCI0_MEM_BASE   0x80000000
  62
  63 static void setup_pcicfg_window(void)
  64 {
  65         if (pcicfg_ioh)
  66                 return;
  67         if (bus_space_init(&pcicfg_tag,
  68             "pcicfg", ex_storage, sizeof(ex_storage)) ||
  69             bus_space_map(pcicfg_iot, 0, 0x40 , 0, &pcicfg_ioh))
  70                 panic("Cannot map PCI configuration registers");
  71 }
  72
  73 /*
  74  * Setup proper Local<->PCI mapping
  75  * PCI memory window: 256M @ PCI0MEMBASE with direct memory translation
  76  */
  77 void ibm4xx_setup_pci(void)
  78 {
  79         pcitag_t tag;
  80
  81         setup_pcicfg_window();
  82
  83         /* Disable all three memory mappers */
  84         bus_space_write_4(pcicfg_iot, pcicfg_ioh, PCIL_PMM0MA, 0x00000000); /* disabled */
  85         bus_space_write_4(pcicfg_iot, pcicfg_ioh, PCIL_PMM1MA, 0x00000000); /* disabled */
  86         bus_space_write_4(pcicfg_iot, pcicfg_ioh, PCIL_PMM2MA, 0x00000000); /* disabled */
  87         bus_space_write_4(pcicfg_iot, pcicfg_ioh, PCIL_PTM1MS, 0x00000000); /* Can't really disable PTM1. */
  88         bus_space_write_4(pcicfg_iot, pcicfg_ioh, PCIL_PTM2MS, 0x00000000); /* disabled */
  89
  90
  91         /* Setup memory map #0 */
  92         bus_space_write_4(pcicfg_iot, pcicfg_ioh, PCIL_PMM0MA, 0xF0000001); /* 256M non-prefetchable, enabled */
  93
  94         bus_space_write_4(pcicfg_iot, pcicfg_ioh, PCIL_PMM0LA, PCI0_MEM_BASE);
  95         bus_space_write_4(pcicfg_iot, pcicfg_ioh, PCIL_PMM0PCILA, PCI0_MEM_BASE);
  96         bus_space_write_4(pcicfg_iot, pcicfg_ioh, PCIL_PMM0PCIHA, 0);
  97
  98         /* Configure PCI bridge */
  99         tag = pci_make_tag(0, 0, 0, 0);
 100         // x = pci_conf_read(0, tag, PCI0_CMD);         /* Read PCI command register */
 101         // pci_conf_write(0, tag, PCI0_CMD, x | MA | ME);       /* enable bus mastering and memory space */
 102
 103         bus_space_write_4(pcicfg_iot, pcicfg_ioh, PCIL_PTM1MS, 0xF0000001);     /* Enable PTM1 */
 104         bus_space_write_4(pcicfg_iot, pcicfg_ioh, PCIL_PTM1LA, 0);
 105         pci_conf_write(0, tag, PCIC_PTM1BAR, 0);        /* Set up proper PCI->Local address base.  Always enabled */
 106         pci_conf_write(0, tag, PCIC_PTM2BAR, 0);
 107 }
 108
 109 void ibm4xx_show_pci_map(void)
 110 {
 111         paddr_t la, lm, pl, ph;
 112         pcitag_t tag;
 113
 114         setup_pcicfg_window();
 115
 116         printf("Local -> PCI map\n");
 117         la = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PCIL_PMM0LA);
 118         lm = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PCIL_PMM0MA);
 119         pl = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PCIL_PMM0PCILA);
 120         ph = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PCIL_PMM0PCIHA);
 121         printf("0: %08lx,%08lx -> %08lx%08lx %sprefetchable, %s\n", la, lm, ph, pl,
 122             (lm & 2) ? "":"not ",
 123             (lm & 1) ? "enabled":"disabled");
 124         la = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PCIL_PMM1LA);
 125         lm = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PCIL_PMM1MA);
 126         pl = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PCIL_PMM1PCILA);
 127         ph = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PCIL_PMM1PCIHA);
 128         printf("1: %08lx,%08lx -> %08lx%08lx %sprefetchable, %s\n", la, lm, ph, pl,
 129             (lm & 2) ? "":"not ",
 130             (lm & 1) ? "enabled":"disabled");
 131         la = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PCIL_PMM2LA);
 132         lm = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PCIL_PMM2MA);
 133         pl = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PCIL_PMM2PCILA);
 134         ph = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PCIL_PMM2PCIHA);
 135         printf("2: %08lx,%08lx -> %08lx%08lx %sprefetchable, %s\n", la, lm, ph, pl,
 136             (lm & 2) ? "":"not ",
 137             (lm & 1) ? "enabled":"disabled");
 138         printf("PCI -> Local map\n");
 139
 140         tag = pci_make_tag(0, 0, 0, 0);
 141         pl = pci_conf_read(0, tag, PCIC_PTM1BAR);
 142         la = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PCIL_PTM1LA);
 143         lm = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PCIL_PTM1MS);
 144         printf("1: %08lx -> %08lx,%08lx %s\n", pl, la, lm,
 145             (lm & 1)?"enabled":"disabled");
 146         pl = pci_conf_read(0, tag, PCIC_PTM2BAR);
 147         la = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PCIL_PTM2LA);
 148         lm = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PCIL_PTM2MS);
 149         printf("2: %08lx -> %08lx,%08lx %s\n", pl, la, lm,
 150             (lm & 1)?"enabled":"disabled");
 151 }