sys/arch/powerpc/ibm4xx/intr.c

   1 /*      $NetBSD: intr.c,v 1.20 2008/01/02 11:48:27 ad Exp $     */
   2
   3 /*
   4  * Copyright 2002 Wasabi Systems, Inc.
   5  * All rights reserved.
   6  *
   7  * Written by Eduardo Horvath and Simon Burge for Wasabi Systems, Inc.
   8  *
   9  * Redistribution and use in source and binary forms, with or without
  10  * modification, are permitted provided that the following conditions
  11  * are met:
  12  * 1. Redistributions of source code must retain the above copyright
  13  *    notice, this list of conditions and the following disclaimer.
  14  * 2. Redistributions in binary form must reproduce the above copyright
  15  *    notice, this list of conditions and the following disclaimer in the
  16  *    documentation and/or other materials provided with the distribution.
  17  * 3. All advertising materials mentioning features or use of this software
  18  *    must display the following acknowledgement:
  19  *      This product includes software developed for the NetBSD Project by
  20  *      Wasabi Systems, Inc.
  21  * 4. The name of Wasabi Systems, Inc. may not be used to endorse
  22  *    or promote products derived from this software without specific prior
  23  *    written permission.
  24  *
  25  * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
  26  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  27  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  28  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
  29  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  30  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  31  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  32  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  33  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  34  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  35  * POSSIBILITY OF SUCH DAMAGE.
  36  */
  37
  38 #include <sys/cdefs.h>
  39 __KERNEL_RCSID(0, "$NetBSD: intr.c,v 1.20 2008/01/02 11:48:27 ad Exp $");
  40
  41 #include <sys/param.h>
  42 #include <sys/malloc.h>
  43 #include <sys/kernel.h>
  44 #include <sys/evcnt.h>
  45
  46 #include <uvm/uvm_extern.h>
  47
  48 #include <machine/intr.h>
  49 #include <machine/psl.h>
  50
  51 #include <powerpc/cpu.h>
  52 #include <powerpc/spr.h>
  53
  54
  55 /*
  56  * Number of interrupts (hard + soft), irq number legality test,
  57  * mapping of irq number to mask and a way to pick irq number
  58  * off a mask of active intrs.
  59  */
  60 #define ICU_LEN                 32
  61 #define LEGAL_IRQ(x)            ((x) >= 0 && (x) < ICU_LEN)
  62
  63 #define IRQ_TO_MASK(irq)        (0x80000000UL >> (irq))
  64 #define IRQ_OF_MASK(mask)       cntlzw(mask)
  65
  66 /*
  67  * Assign these to unused (reserved) interrupt bits.
  68  *
  69  * For 405GP (and 403CGX?) interrupt bits 0-18 and 25-31 are used
  70  * by hardware.  This leaves us bits 19-24 for software.
  71  */
  72 #define IRQ_SOFTNET     19
  73 #define IRQ_SOFTCLOCK   20
  74 #define IRQ_SOFTSERIAL  21
  75 #define IRQ_CLOCK       22
  76 #define IRQ_STATCLOCK   23
  77
  78 /*
  79  * Platform specific code may override any of the above.
  80  */
  81 #ifdef PPC_IBM403
  82
  83 #include <powerpc/ibm4xx/dcr403cgx.h>
  84 #define INTR_STATUS     DCR_EXISR
  85 #define INTR_ACK        DCR_EXISR
  86 #define INTR_ENABLE     DCR_EXIER
  87
  88 #elif defined(__virtex__)
  89
  90 #include <evbppc/virtex/dev/xintcreg.h>
  91 #define INTR_STATUS     XINTC_ISR
  92 #define INTR_ACK        XINTC_IAR
  93 #define INTR_ENABLE     XINTC_IER
  94 #define INTR_MASTER     XINTC_MER
  95 #define INTR_MASTER_EN  (MER_HIE|MER_ME)
  96 #undef  IRQ_TO_MASK
  97 #undef  IRQ_OF_MASK
  98 #undef  IRQ_SOFTNET
  99 #undef  IRQ_SOFTCLOCK
 100 #undef  IRQ_SOFTSERIAL
 101 #undef  IRQ_CLOCK
 102 #undef  IRQ_STATCLOCK
 103 #define IRQ_TO_MASK(i)  (1 << (i))              /* Redefine mappings */
 104 #define IRQ_OF_MASK(m)  (31 - cntlzw(m))
 105 #define IRQ_SOFTNET     31                      /* Redefine "unused" pins */
 106 #define IRQ_SOFTCLOCK   30
 107 #define IRQ_SOFTSERIAL  29
 108 #define IRQ_CLOCK       28
 109 #define IRQ_STATCLOCK   27
 110
 111 #else /* Generic 405 Universal Interrupt Controller */
 112
 113 #include <powerpc/ibm4xx/dcr405gp.h>
 114 #define INTR_STATUS     DCR_UIC0_MSR
 115 #define INTR_ACK        DCR_UIC0_SR
 116 #define INTR_ENABLE     DCR_UIC0_ER
 117
 118 #endif
 119
 120 #define MASK_SOFTNET    IRQ_TO_MASK(IRQ_SOFTNET)
 121 #define MASK_SOFTCLOCK  IRQ_TO_MASK(IRQ_SOFTCLOCK)
 122 #define MASK_SOFTSERIAL IRQ_TO_MASK(IRQ_SOFTSERIAL)
 123 #define MASK_STATCLOCK  IRQ_TO_MASK(IRQ_STATCLOCK)
 124 #define MASK_CLOCK      (IRQ_TO_MASK(IRQ_CLOCK) | IRQ_TO_MASK(IRQ_STATCLOCK))
 125 #define MASK_SOFTINTR   (MASK_SOFTCLOCK|MASK_SOFTNET|MASK_SOFTSERIAL)
 126 #define MASK_HARDINTR   ~(MASK_SOFTINTR|MASK_CLOCK)
 127
 128 static inline void disable_irq(int);
 129 static inline void enable_irq(int);
 130 static void intr_calculatemasks(void);
 131 static void do_pending_int(void);
 132 static const char *intr_typename(int);
 133
 134
 135 /*
 136  * Interrupt handler chains.  intr_establish() inserts a handler into
 137  * the list.  The handler is called with its (single) argument.
 138  */
 139 struct intrhand {
 140         int                     (*ih_fun)(void *);
 141         void                    *ih_arg;
 142         struct  intrhand        *ih_next;
 143         int                     ih_level;
 144 };
 145
 146 struct intrsrc {
 147         struct evcnt            is_evcnt;
 148         struct intrhand         *is_head;
 149         u_int                   is_mask;
 150         int                     is_level;       /* spls bitmask */
 151         int                     is_type;        /* sensitivity */
 152 };
 153
 154
 155 volatile u_int                  imask[NIPL];
 156 const int                       mask_clock = MASK_CLOCK;
 157 const int                       mask_statclock = MASK_STATCLOCK;
 158
 159 static struct intrsrc           intrs[ICU_LEN] = {
 160 #define DEFINTR(name)           \
 161         { EVCNT_INITIALIZER(EVCNT_TYPE_INTR, NULL, "uic", name), NULL, 0, 0 }
 162
 163         DEFINTR("pin0"),        DEFINTR("pin1"),        DEFINTR("pin2"),
 164         DEFINTR("pin3"),        DEFINTR("pin4"),        DEFINTR("pin5"),
 165         DEFINTR("pin6"),        DEFINTR("pin7"),        DEFINTR("pin8"),
 166         DEFINTR("pin9"),        DEFINTR("pin10"),       DEFINTR("pin11"),
 167         DEFINTR("pin12"),       DEFINTR("pin13"),       DEFINTR("pin14"),
 168         DEFINTR("pin15"),       DEFINTR("pin16"),       DEFINTR("pin17"),
 169         DEFINTR("pin18"),
 170
 171         /* Reserved intrs, accounted in cpu_info */
 172         DEFINTR(NULL),          /* unused "pin19", softnet */
 173         DEFINTR(NULL),          /* unused "pin20", softclock */
 174         DEFINTR(NULL),          /* unused "pin21", softserial */
 175         DEFINTR(NULL),          /* unused "pin22", PIT hardclock */
 176         DEFINTR(NULL),          /* unused "pin23", FIT statclock */
 177
 178         DEFINTR("pin24"),       DEFINTR("pin25"),       DEFINTR("pin26"),
 179         DEFINTR("pin27"),       DEFINTR("pin28"),       DEFINTR("pin29"),
 180         DEFINTR("pin30"),       DEFINTR("pin31")
 181
 182 #undef DEFINTR
 183 };
 184
 185
 186 /* Write External Enable Immediate */
 187 #define wrteei(en)              __asm volatile ("wrteei %0" : : "K"(en))
 188
 189 /* Enforce In Order Execution Of I/O */
 190 #define eieio()                 __asm volatile ("eieio")
 191
 192 /*
 193  * Set up interrupt mapping array.
 194  */
 195 void
 196 intr_init(void)
 197 {
 198         int i;
 199
 200         for (i = 0; i < ICU_LEN; i++)
 201                 switch (i) {
 202                 case IRQ_SOFTNET:
 203                 case IRQ_SOFTCLOCK:
 204                 case IRQ_SOFTSERIAL:
 205                 case IRQ_CLOCK:
 206                 case IRQ_STATCLOCK:
 207                         continue;
 208                 default:
 209                         evcnt_attach_static(&intrs[i].is_evcnt);
 210                 }
 211
 212         /* Initialized in powerpc/ibm4xx/cpu.c */
 213         evcnt_attach_static(&curcpu()->ci_ev_softclock);
 214         evcnt_attach_static(&curcpu()->ci_ev_softnet);
 215         evcnt_attach_static(&curcpu()->ci_ev_softserial);
 216
 217         mtdcr(INTR_ENABLE, 0x00000000);         /* mask all */
 218         mtdcr(INTR_ACK, 0xffffffff);            /* acknowledge all */
 219 #ifdef INTR_MASTER
 220         mtdcr(INTR_MASTER, INTR_MASTER_EN);     /* enable controller */
 221 #endif
 222 }
 223
 224 /*
 225  * external interrupt handler
 226  */
 227 void
 228 ext_intr(void)
 229 {
 230         struct cpu_info *ci = curcpu();
 231         struct intrhand *ih;
 232         int i, bits_to_clear;
 233         int r_imen, msr;
 234         int pcpl;
 235         u_long int_state;
 236
 237         pcpl = ci->ci_cpl;
 238         msr = mfmsr();
 239
 240         int_state = mfdcr(INTR_STATUS); /* Read non-masked interrupt status */
 241         bits_to_clear = int_state;
 242
 243         while (int_state) {
 244                 i = IRQ_OF_MASK(int_state);
 245
 246                 r_imen = IRQ_TO_MASK(i);
 247                 int_state &= ~r_imen;
 248
 249                 if ((pcpl & r_imen) != 0) {
 250                         /* Masked! Mark as pending */
 251                         ci->ci_ipending |= r_imen;
 252                         disable_irq(i);
 253                 } else {
 254                         ci->ci_idepth++;
 255                         splraise(intrs[i].is_mask);
 256                         if (intrs[i].is_type == IST_LEVEL)
 257                                 disable_irq(i);
 258                         wrteei(1);
 259
 260                         ih = intrs[i].is_head;
 261                         while (ih) {
 262                                 if (ih->ih_level == IPL_VM)
 263                                         KERNEL_LOCK(1, NULL);
 264                                 (*ih->ih_fun)(ih->ih_arg);
 265                                 ih = ih->ih_next;
 266                                 if (ih->ih_level == IPL_VM)
 267                                         KERNEL_UNLOCK_ONE(NULL);
 268                         }
 269
 270                         mtmsr(msr);
 271                         if (intrs[i].is_type == IST_LEVEL)
 272                                 enable_irq(i);
 273                         ci->ci_cpl = pcpl;
 274                         uvmexp.intrs++;
 275                         intrs[i].is_evcnt.ev_count++;
 276                         ci->ci_idepth--;
 277                 }
 278         }
 279         mtdcr(INTR_ACK, bits_to_clear); /* Acknowledge all pending interrupts */
 280
 281         wrteei(1);
 282         splx(pcpl);
 283         mtmsr(msr);
 284 }
 285
 286 static inline void
 287 disable_irq(int irq)
 288 {
 289         int mask, omask;
 290
 291         mask = omask = mfdcr(INTR_ENABLE);
 292         mask &= ~IRQ_TO_MASK(irq);
 293         if (mask == omask)
 294                 return;
 295         mtdcr(INTR_ENABLE, mask);
 296 #ifdef IRQ_DEBUG
 297         printf("irq_disable: irq=%d, mask=%08x\n",irq,mask);
 298 #endif
 299 }
 300
 301 static inline void
 302 enable_irq(int irq)
 303 {
 304         int mask, omask;
 305
 306         mask = omask = mfdcr(INTR_ENABLE);
 307         mask |= IRQ_TO_MASK(irq);
 308         if (mask == omask)
 309                 return;
 310         mtdcr(INTR_ENABLE, mask);
 311 #ifdef IRQ_DEBUG
 312         printf("enable_irq: irq=%d, mask=%08x\n",irq,mask);
 313 #endif
 314 }
 315
 316 static const char *
 317 intr_typename(int type)
 318 {
 319
 320         switch (type) {
 321         case IST_NONE :
 322                 return ("none");
 323         case IST_PULSE:
 324                 return ("pulsed");
 325         case IST_EDGE:
 326                 return ("edge-triggered");
 327         case IST_LEVEL:
 328                 return ("level-triggered");
 329         default:
 330                 panic("intr_typename: invalid type %d", type);
 331         }
 332 }
 333
 334 /*
 335  * Register an interrupt handler.
 336  */
 337 void *
 338 intr_establish(int irq, int type, int level, int (*ih_fun)(void *),
 339     void *ih_arg)
 340 {
 341         struct intrhand *ih;
 342         int msr;
 343
 344         if (! LEGAL_IRQ(irq))
 345                 panic("intr_establish: bogus irq %d", irq);
 346
 347         if (type == IST_NONE)
 348                 panic("intr_establish: bogus type %d for irq %d", type, irq);
 349
 350         /* No point in sleeping unless someone can free memory. */
 351         ih = malloc(sizeof *ih, M_DEVBUF, cold ? M_NOWAIT : M_WAITOK);
 352         if (ih == NULL)
 353                 panic("intr_establish: can't malloc handler info");
 354
 355         switch (intrs[irq].is_type) {
 356         case IST_NONE:
 357                 intrs[irq].is_type = type;
 358                 break;
 359
 360         case IST_EDGE:
 361         case IST_LEVEL:
 362                 if (type == intrs[irq].is_type)
 363                         break;
 364                 /* FALLTHROUGH */
 365
 366         case IST_PULSE:
 367                 if (type != IST_NONE)
 368                         panic("intr_establish: can't share %s with %s",
 369                             intr_typename(intrs[irq].is_type),
 370                             intr_typename(type));
 371                 break;
 372         }
 373
 374         /*
 375          * We're not on critical paths, so just block intrs for a while.
 376          * Note that spl*() at this point would use old (wrong) masks.
 377          */
 378         msr = mfmsr();
 379         wrteei(0);
 380
 381         /*
 382          * Poke the real handler in now. We deliberately don't preserve order,
 383          * the user is not allowed to make any assumptions about it anyway.
 384          */
 385         ih->ih_fun = ih_fun;
 386         ih->ih_arg = ih_arg;
 387         ih->ih_level = level;
 388         ih->ih_next = intrs[irq].is_head;
 389         intrs[irq].is_head = ih;
 390
 391         intr_calculatemasks();
 392
 393         eieio();
 394         mtmsr(msr);
 395
 396 #ifdef IRQ_DEBUG
 397         printf("***** intr_establish: irq%d h=%p arg=%p\n",irq, ih_fun, ih_arg);
 398 #endif
 399         return (ih);
 400 }
 401
 402 /*
 403  * Deregister an interrupt handler.
 404  */
 405 void
 406 intr_disestablish(void *arg)
 407 {
 408         struct intrhand *ih = arg;
 409         struct intrhand **p;
 410         int i, msr;
 411
 412         /* Lookup the handler. This is expensive, but not run often. */
 413         for (i = 0; i < ICU_LEN; i++)
 414                 for (p = &intrs[i].is_head; *p != NULL; p = &(*p)->ih_next)
 415                         if (*p == ih)
 416                                 goto out;
 417  out:
 418         if (i == ICU_LEN)
 419                 panic("intr_disestablish: handler not registered");
 420
 421         *p = ih->ih_next;
 422         free(ih, M_DEVBUF);
 423
 424         msr = mfmsr();
 425         wrteei(0);
 426         intr_calculatemasks();
 427         mtmsr(msr);
 428
 429         if (intrs[i].is_head == NULL)
 430                 intrs[i].is_type = IST_NONE;
 431 }
 432
 433 /*
 434  * Recalculate the interrupt masks from scratch.
 435  * We could code special registry and deregistry versions of this function that
 436  * would be faster, but the code would be nastier, and we don't expect this to
 437  * happen very much anyway. We assume PSL_EE is clear when we're called.
 438  */
 439 static void
 440 intr_calculatemasks(void)
 441 {
 442         struct intrhand *q;
 443         int irq, level;
 444
 445         /* First, figure out which levels each IRQ uses. */
 446         for (irq = 0; irq < ICU_LEN; irq++) {
 447                 register int levels = 0;
 448                 for (q = intrs[irq].is_head; q; q = q->ih_next)
 449                         levels |= 1 << q->ih_level;
 450                 intrs[irq].is_level = levels;
 451         }
 452
 453         /* Then figure out which IRQs use each level. */
 454         for (level = 0; level < NIPL; level++) {
 455                 register int irqs = 0;
 456                 for (irq = 0; irq < ICU_LEN; irq++)
 457                         if (intrs[irq].is_level & (1 << level))
 458                                 irqs |= IRQ_TO_MASK(irq);
 459                 imask[level] = irqs | MASK_SOFTINTR;
 460         }
 461
 462         /*
 463          * Enforce a hierarchy that gives slow devices a better chance at not
 464          * dropping data.
 465          */
 466
 467         /*
 468          * Initialize the soft interrupt masks to block themselves.
 469          */
 470         imask[IPL_NONE] = 0;
 471         imask[IPL_SOFTCLOCK] |= MASK_SOFTCLOCK;
 472         imask[IPL_SOFTNET] |= imask[IPL_SOFTCLOCK] | MASK_SOFTNET;
 473         imask[IPL_SOFTSERIAL] = imask[IPL_SOFTNET] | MASK_SOFTSERIAL;
 474         imask[IPL_VM] |= imask[IPL_SOFTSERIAL];
 475         imask[IPL_SCHED] = imask[IPL_VM] | MASK_CLOCK | MASK_STATCLOCK;
 476         imask[IPL_HIGH] |= imask[IPL_SCHED];
 477
 478         /* And eventually calculate the complete masks. */
 479         for (irq = 0; irq < ICU_LEN; irq++) {
 480                 register int irqs = IRQ_TO_MASK(irq);
 481                 for (q = intrs[irq].is_head; q; q = q->ih_next)
 482                         irqs |= imask[q->ih_level];
 483                 intrs[irq].is_mask = irqs;
 484         }
 485
 486         for (irq = 0; irq < ICU_LEN; irq++)
 487                 if (intrs[irq].is_head != NULL)
 488                         enable_irq(irq);
 489                 else
 490                         disable_irq(irq);
 491 }
 492
 493 static void
 494 do_pending_int(void)
 495 {
 496         struct cpu_info *ci = curcpu();
 497         struct intrhand *ih;
 498         int irq;
 499         int pcpl;
 500         int hwpend;
 501         int emsr;
 502
 503         if (ci->ci_idepth)
 504                 return;
 505 #ifdef __HAVE_FAST_SOFTINTS
 506 #error don't count soft interrupts
 507 #else
 508         ci->ci_idepth++;
 509 #endif
 510         emsr = mfmsr();
 511         wrteei(0);
 512
 513         pcpl = ci->ci_cpl;      /* Turn off all */
 514 #ifdef __HAVE_FAST_SOFTINTS
 515   again:
 516 #endif
 517         while ((hwpend = ci->ci_ipending & ~pcpl & MASK_HARDINTR) != 0) {
 518                 irq = IRQ_OF_MASK(hwpend);
 519                 if (intrs[irq].is_type != IST_LEVEL)
 520                         enable_irq(irq);
 521
 522                 ci->ci_ipending &= ~IRQ_TO_MASK(irq);
 523
 524                 splraise(intrs[irq].is_mask);
 525                 mtmsr(emsr);
 526
 527                 ih = intrs[irq].is_head;
 528                 while(ih) {
 529                         if (ih->ih_level == IPL_VM)
 530                                 KERNEL_LOCK(1, NULL);
 531                         (*ih->ih_fun)(ih->ih_arg);
 532                         if (ih->ih_level == IPL_VM)
 533                                 KERNEL_UNLOCK_ONE(NULL);
 534                         ih = ih->ih_next;
 535                 }
 536
 537                 wrteei(0);
 538                 if (intrs[irq].is_type == IST_LEVEL)
 539                         enable_irq(irq);
 540                 ci->ci_cpl = pcpl;
 541                 intrs[irq].is_evcnt.ev_count++;
 542         }
 543 #ifdef __HAVE_FAST_SOFTINTS
 544         if ((ci->ci_ipending & ~pcpl) & MASK_SOFTSERIAL) {
 545                 ci->ci_ipending &= ~MASK_SOFTSERIAL;
 546                 splsoftserial();
 547                 mtmsr(emsr);
 548                 softintr__run(IPL_SOFTSERIAL);
 549                 wrteei(0);
 550                 ci->ci_cpl = pcpl;
 551                 ci->ci_ev_softserial.ev_count++;
 552                 goto again;
 553         }
 554         if ((ci->ci_ipending & ~pcpl) & MASK_SOFTNET) {
 555                 ci->ci_ipending &= ~MASK_SOFTNET;
 556                 splsoftnet();
 557                 mtmsr(emsr);
 558                 softintr__run(IPL_SOFTNET);
 559                 wrteei(0);
 560                 ci->ci_cpl = pcpl;
 561                 ci->ci_ev_softnet.ev_count++;
 562                 goto again;
 563         }
 564         if ((ci->ci_ipending & ~pcpl) & MASK_SOFTCLOCK) {
 565                 ci->ci_ipending &= ~MASK_SOFTCLOCK;
 566                 splsoftclock();
 567                 mtmsr(emsr);
 568                 softintr__run(IPL_SOFTCLOCK);
 569                 wrteei(0);
 570                 ci->ci_cpl = pcpl;
 571                 ci->ci_ev_softclock.ev_count++;
 572                 goto again;
 573         }
 574 #endif
 575         ci->ci_cpl = pcpl; /* Don't use splx... we are here already! */
 576         mtmsr(emsr);
 577         ci->ci_idepth--;
 578 }
 579
 580 #ifdef __HAVE_FAST_SOFTINTS
 581 void
 582 softintr(int idx)
 583 {
 584         static const int softmap[3] = {
 585                 MASK_SOFTCLOCK, MASK_SOFTNET, MASK_SOFTSERIAL
 586         };
 587         int oldmsr;
 588
 589         KASSERT(idx >= 0 && idx < 3);
 590
 591         /*
 592          * This could be implemented with lwarx/stwcx to avoid the
 593          * disable/enable...
 594          */
 595
 596         oldmsr = mfmsr();
 597         wrteei(0);
 598
 599         curcpu()->ci_ipending |= softmap[idx];
 600
 601         mtmsr(oldmsr);
 602 }
 603 #endif
 604
 605 int
 606 splraise(int newcpl)
 607 {
 608         struct cpu_info *ci = curcpu();
 609         int oldcpl, oldmsr;
 610
 611         /*
 612          * We're about to block some intrs, so make sure they don't
 613          * fire while we're busy.
 614          */
 615
 616         oldmsr = mfmsr();
 617         wrteei(0);
 618
 619         oldcpl = ci->ci_cpl;
 620         ci->ci_cpl |= newcpl;
 621
 622         mtmsr(oldmsr);
 623         return (oldcpl);
 624 }
 625
 626 void
 627 splx(int newcpl)
 628 {
 629         struct cpu_info *ci = curcpu();
 630
 631         ci->ci_cpl = newcpl;
 632         if (ci->ci_ipending & ~newcpl)
 633                 do_pending_int();
 634 }
 635
 636 int
 637 spllower(int newcpl)
 638 {
 639         struct cpu_info *ci = curcpu();
 640         int oldcpl;
 641
 642         oldcpl = ci->ci_cpl;
 643         ci->ci_cpl = newcpl;
 644         if (ci->ci_ipending & ~newcpl)
 645                 do_pending_int();
 646
 647         return (oldcpl);
 648 }