sys/arch/powerpc/include/cpu.h

   1 /*      $NetBSD: cpu.h,v 1.66 2009/10/21 21:12:01 rmind Exp $   */
   2
   3 /*
   4  * Copyright (C) 1999 Wolfgang Solfrank.
   5  * Copyright (C) 1999 TooLs GmbH.
   6  * Copyright (C) 1995-1997 Wolfgang Solfrank.
   7  * Copyright (C) 1995-1997 TooLs GmbH.
   8  * All rights reserved.
   9  *
  10  * Redistribution and use in source and binary forms, with or without
  11  * modification, are permitted provided that the following conditions
  12  * are met:
  13  * 1. Redistributions of source code must retain the above copyright
  14  *    notice, this list of conditions and the following disclaimer.
  15  * 2. Redistributions in binary form must reproduce the above copyright
  16  *    notice, this list of conditions and the following disclaimer in the
  17  *    documentation and/or other materials provided with the distribution.
  18  * 3. All advertising materials mentioning features or use of this software
  19  *    must display the following acknowledgement:
  20  *      This product includes software developed by TooLs GmbH.
  21  * 4. The name of TooLs GmbH may not be used to endorse or promote products
  22  *    derived from this software without specific prior written permission.
  23  *
  24  * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
  25  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  26  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  27  * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  28  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  29  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
  30  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  31  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
  32  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
  33  * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  34  */
  35 #ifndef _POWERPC_CPU_H_
  36 #define _POWERPC_CPU_H_
  37
  38 struct cache_info {
  39         int dcache_size;
  40         int dcache_line_size;
  41         int icache_size;
  42         int icache_line_size;
  43 };
  44
  45 #ifdef _KERNEL
  46 #if defined(_KERNEL_OPT)
  47 #include "opt_lockdebug.h"
  48 #include "opt_multiprocessor.h"
  49 #include "opt_ppcarch.h"
  50 #endif
  51
  52 #include <machine/frame.h>
  53 #include <machine/psl.h>
  54 #include <machine/intr.h>
  55 #include <sys/device.h>
  56
  57 #include <sys/cpu_data.h>
  58
  59 struct cpu_info {
  60         struct cpu_data ci_data;        /* MI per-cpu data */
  61         struct device *ci_dev;          /* device of corresponding cpu */
  62         struct lwp *ci_curlwp;          /* current owner of the processor */
  63
  64         struct pcb *ci_curpcb;
  65         struct pmap *ci_curpm;
  66         struct lwp *ci_fpulwp;
  67         struct lwp *ci_veclwp;
  68         int ci_cpuid;
  69
  70         volatile int ci_astpending;
  71         int ci_want_resched;
  72         volatile u_long ci_lasttb;
  73         volatile int ci_tickspending;
  74         volatile int ci_cpl;
  75         volatile int ci_iactive;
  76         volatile int ci_idepth;
  77         volatile int ci_ipending;
  78         int ci_intrdepth;
  79         int ci_mtx_oldspl;
  80         int ci_mtx_count;
  81         char *ci_intstk;
  82 #define CPUSAVE_LEN     8
  83         register_t ci_tempsave[CPUSAVE_LEN];
  84         register_t ci_ddbsave[CPUSAVE_LEN];
  85         register_t ci_ipkdbsave[CPUSAVE_LEN];
  86 #define CPUSAVE_R28     0               /* where r28 gets saved */
  87 #define CPUSAVE_R29     1               /* where r29 gets saved */
  88 #define CPUSAVE_R30     2               /* where r30 gets saved */
  89 #define CPUSAVE_R31     3               /* where r31 gets saved */
  90 #define CPUSAVE_DAR     4               /* where SPR_DAR gets saved */
  91 #define CPUSAVE_DSISR   5               /* where SPR_DSISR gets saved */
  92 #define CPUSAVE_SRR0    6               /* where SRR0 gets saved */
  93 #define CPUSAVE_SRR1    7               /* where SRR1 gets saved */
  94 #define DISISAVE_LEN    4
  95         register_t ci_disisave[DISISAVE_LEN];
  96         struct cache_info ci_ci;
  97         void *ci_sysmon_cookie;
  98         void (*ci_idlespin)(void);
  99         uint32_t ci_khz;
 100         struct evcnt ci_ev_clock;       /* clock intrs */
 101         struct evcnt ci_ev_statclock;   /* stat clock */
 102         struct evcnt ci_ev_softclock;   /* softclock intrs */
 103         struct evcnt ci_ev_softnet;     /* softnet intrs */
 104         struct evcnt ci_ev_softserial;  /* softserial intrs */
 105         struct evcnt ci_ev_traps;       /* calls to trap() */
 106         struct evcnt ci_ev_kdsi;        /* kernel DSI traps */
 107         struct evcnt ci_ev_udsi;        /* user DSI traps */
 108         struct evcnt ci_ev_udsi_fatal;  /* user DSI trap failures */
 109         struct evcnt ci_ev_kisi;        /* kernel ISI traps */
 110         struct evcnt ci_ev_isi;         /* user ISI traps */
 111         struct evcnt ci_ev_isi_fatal;   /* user ISI trap failures */
 112         struct evcnt ci_ev_pgm;         /* user PGM traps */
 113         struct evcnt ci_ev_fpu;         /* FPU traps */
 114         struct evcnt ci_ev_fpusw;       /* FPU context switch */
 115         struct evcnt ci_ev_ali;         /* Alignment traps */
 116         struct evcnt ci_ev_ali_fatal;   /* Alignment fatal trap */
 117         struct evcnt ci_ev_scalls;      /* system call traps */
 118         struct evcnt ci_ev_vec;         /* Altivec traps */
 119         struct evcnt ci_ev_vecsw;       /* Altivec context switches */
 120         struct evcnt ci_ev_umchk;       /* user MCHK events */
 121         struct evcnt ci_ev_ipi;         /* IPIs received */
 122 };
 123
 124 #ifdef MULTIPROCESSOR
 125
 126 struct cpu_hatch_data {
 127         struct device *self;
 128         struct cpu_info *ci;
 129         int running;
 130         int pir;
 131         int asr;
 132         int hid0;
 133         int sdr1;
 134         int sr[16];
 135         int batu[4], batl[4];
 136         int tbu, tbl;
 137 };
 138
 139 static __inline int
 140 cpu_number(void)
 141 {
 142         int pir;
 143
 144         __asm ("mfspr %0,1023" : "=r"(pir));
 145         return pir;
 146 }
 147
 148 void    cpu_boot_secondary_processors(void);
 149
 150
 151 #define CPU_IS_PRIMARY(ci)      ((ci)->ci_cpuid == 0)
 152 #define CPU_INFO_ITERATOR               int
 153 #define CPU_INFO_FOREACH(cii, ci)                                       \
 154         cii = 0, ci = &cpu_info[0]; cii < ncpu; cii++, ci++
 155
 156 #else
 157
 158 #define cpu_number()            0
 159
 160 #define CPU_INFO_ITERATOR               int
 161 #define CPU_INFO_FOREACH(cii, ci)                                       \
 162         cii = 0, ci = curcpu(); ci != NULL; ci = NULL
 163
 164 #endif /* MULTIPROCESSOR */
 165
 166 extern struct cpu_info cpu_info[];
 167
 168 static __inline struct cpu_info *
 169 curcpu(void)
 170 {
 171         struct cpu_info *ci;
 172
 173         __asm volatile ("mfsprg %0,0" : "=r"(ci));
 174         return ci;
 175 }
 176
 177 #define curlwp                  (curcpu()->ci_curlwp)
 178 #define curpcb                  (curcpu()->ci_curpcb)
 179 #define curpm                   (curcpu()->ci_curpm)
 180
 181 static __inline register_t
 182 mfmsr(void)
 183 {
 184         register_t msr;
 185
 186         __asm volatile ("mfmsr %0" : "=r"(msr));
 187         return msr;
 188 }
 189
 190 static __inline void
 191 mtmsr(register_t msr)
 192 {
 193
 194         __asm volatile ("mtmsr %0" : : "r"(msr));
 195 }
 196
 197 static __inline uint32_t
 198 mftbl(void)
 199 {
 200         uint32_t tbl;
 201
 202         __asm volatile (
 203 #ifdef PPC_IBM403
 204 "       mftblo %0       \n"
 205 #else
 206 "       mftbl %0        \n"
 207 #endif
 208         : "=r" (tbl));
 209
 210         return tbl;
 211 }
 212
 213 static __inline uint64_t
 214 mftb(void)
 215 {
 216         uint64_t tb;
 217
 218 #ifdef _LP64
 219         __asm volatile ("mftb %0" : "=r"(tb));
 220 #else
 221         int tmp;
 222
 223         __asm volatile (
 224 #ifdef PPC_IBM403
 225 "1:     mftbhi %0       \n"
 226 "       mftblo %0+1     \n"
 227 "       mftbhi %1       \n"
 228 #else
 229 "1:     mftbu %0        \n"
 230 "       mftb %0+1       \n"
 231 "       mftbu %1        \n"
 232 #endif
 233 "       cmplw %0,%1     \n"
 234 "       bne- 1b         \n"
 235         : "=r" (tb), "=r"(tmp) :: "cr0");
 236 #endif
 237
 238         return tb;
 239 }
 240
 241 static __inline uint32_t
 242 mfrtcl(void)
 243 {
 244         uint32_t rtcl;
 245
 246         __asm volatile ("mfrtcl %0" : "=r"(rtcl));
 247         return rtcl;
 248 }
 249
 250 static __inline void
 251 mfrtc(uint32_t *rtcp)
 252 {
 253         uint32_t tmp;
 254
 255         __asm volatile (
 256 "1:     mfrtcu  %0      \n"
 257 "       mfrtcl  %1      \n"
 258 "       mfrtcu  %2      \n"
 259 "       cmplw   %0,%2   \n"
 260 "       bne-    1b"
 261             : "=r"(*rtcp), "=r"(*(rtcp + 1)), "=r"(tmp) :: "cr0");
 262 }
 263
 264 static __inline uint32_t
 265 mfpvr(void)
 266 {
 267         uint32_t pvr;
 268
 269         __asm volatile ("mfpvr %0" : "=r"(pvr));
 270         return (pvr);
 271 }
 272
 273 static __inline int
 274 cntlzw(uint32_t val)
 275 {
 276         int                     cnt;
 277
 278         __asm volatile ("cntlzw %0,%1" : "=r"(cnt) : "r"(val));
 279         return (cnt);
 280 }
 281
 282 #if defined(PPC_IBM4XX) || defined(PPC_IBM403)
 283 /*
 284  * DCR (Device Control Register) access. These have to be
 285  * macros because register address is encoded as immediate
 286  * operand.
 287  */
 288 #define mtdcr(reg, val)                                         \
 289         __asm volatile("mtdcr %0,%1" : : "K"(reg), "r"(val))
 290
 291 #define mfdcr(reg)                                              \
 292 ({                                                              \
 293         uint32_t __val;                                         \
 294                                                                 \
 295         __asm volatile("mfdcr %0,%1" : "=r"(__val) : "K"(reg)); \
 296         __val;                                                  \
 297 })
 298 #endif /* PPC_IBM4XX || PPC_IBM403 */
 299
 300 #define CLKF_USERMODE(frame)    (((frame)->srr1 & PSL_PR) != 0)
 301 #define CLKF_PC(frame)          ((frame)->srr0)
 302 #define CLKF_INTR(frame)        ((frame)->depth > 0)
 303
 304 #define LWP_PC(l)               (trapframe(l)->srr0)
 305
 306 #define cpu_proc_fork(p1, p2)
 307 #define cpu_idle()              (curcpu()->ci_idlespin())
 308
 309 extern int powersave;
 310 extern int cpu_timebase;
 311 extern int cpu_printfataltraps;
 312 extern char cpu_model[];
 313
 314 struct cpu_info *cpu_attach_common(struct device *, int);
 315 void cpu_setup(struct device *, struct cpu_info *);
 316 void cpu_identify(char *, size_t);
 317 void delay (unsigned int);
 318 void cpu_probe_cache(void);
 319 void dcache_flush_page(vaddr_t);
 320 void icache_flush_page(vaddr_t);
 321 void dcache_flush(vaddr_t, vsize_t);
 322 void icache_flush(vaddr_t, vsize_t);
 323 void *mapiodev(paddr_t, psize_t);
 324 void unmapiodev(vaddr_t, vsize_t);
 325
 326 #ifdef MULTIPROCESSOR
 327 int md_setup_trampoline(volatile struct cpu_hatch_data *, struct cpu_info *);
 328 void md_presync_timebase(volatile struct cpu_hatch_data *);
 329 void md_start_timebase(volatile struct cpu_hatch_data *);
 330 void md_sync_timebase(volatile struct cpu_hatch_data *);
 331 void md_setup_interrupts(void);
 332 int cpu_spinup(struct device *, struct cpu_info *);
 333 register_t cpu_hatch(void);
 334 void cpu_spinup_trampoline(void);
 335 #endif
 336
 337 #define DELAY(n)                delay(n)
 338
 339 #define cpu_need_resched(ci, v) (ci->ci_want_resched = ci->ci_astpending = 1)
 340 #define cpu_did_resched(l)      ((void)(curcpu()->ci_want_resched = 0))
 341 #define cpu_need_proftick(l)    ((l)->l_pflag |= LP_OWEUPC, curcpu()->ci_astpending = 1)
 342 #define cpu_signotify(l)        (curcpu()->ci_astpending = 1)   /* XXXSMP */
 343
 344 #if !defined(PPC_IBM4XX)
 345 void oea_init(void (*)(void));
 346 void oea_startup(const char *);
 347 void oea_dumpsys(void);
 348 void oea_install_extint(void (*)(void));
 349 paddr_t kvtop(void *);
 350 void softnet(int);
 351
 352 extern paddr_t msgbuf_paddr;
 353 extern int cpu_altivec;
 354 #endif
 355
 356 #endif /* _KERNEL */
 357
 358 /* XXX The below breaks unified pmap on ppc32 */
 359
 360 #if defined(_KERNEL) || defined(_STANDALONE)
 361 #if !defined(CACHELINESIZE)
 362 #ifdef PPC_IBM403
 363 #define CACHELINESIZE           16
 364 #define MAXCACHELINESIZE        16
 365 #else
 366 #if defined (PPC_OEA64_BRIDGE)
 367 #define CACHELINESIZE           128
 368 #define MAXCACHELINESIZE        128
 369 #else
 370 #define CACHELINESIZE           32
 371 #define MAXCACHELINESIZE        32
 372 #endif /* PPC_OEA64_BRIDGE */
 373 #endif
 374 #endif
 375 #endif
 376
 377 void __syncicache(void *, size_t);
 378
 379 /*
 380  * CTL_MACHDEP definitions.
 381  */
 382 #define CPU_CACHELINE           1
 383 #define CPU_TIMEBASE            2
 384 #define CPU_CPUTEMP             3
 385 #define CPU_PRINTFATALTRAPS     4
 386 #define CPU_CACHEINFO           5
 387 #define CPU_ALTIVEC             6
 388 #define CPU_MODEL               7
 389 #define CPU_POWERSAVE           8       /* int: use CPU powersave mode */
 390 #define CPU_BOOTED_DEVICE       9       /* string: device we booted from */
 391 #define CPU_BOOTED_KERNEL       10      /* string: kernel we booted */
 392 #define CPU_MAXID               11      /* number of valid machdep ids */
 393
 394 #endif  /* _POWERPC_CPU_H_ */