1 /* $NetBSD: mcontext.h,v 1.7 2005/12/11 12:18:43 christos Exp $ */
4 * Copyright (c) 2001 The NetBSD Foundation, Inc.
7 * This code is derived from software contributed to The NetBSD Foundation
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
32 #ifndef _POWERPC_MCONTEXT_H_
33 #define _POWERPC_MCONTEXT_H_
36 * Layout of mcontext_t based on the System V Application Binary Interface,
37 * Edition 4.1, PowerPC Processor ABI Supplement - September 1995, and
38 * extended for the AltiVec Register File. Note that due to the increased
39 * alignment requirements of the latter, the offset of mcontext_t within
40 * an ucontext_t is different from System V.
43 #define _NGREG 39 /* GR0-31, CR, LR, SRR0, SRR1, CTR, XER, MQ */
45 typedef long __greg_t
;
46 typedef __greg_t __gregset_t
[_NGREG
];
80 #define _REG_CR 32 /* Condition Register */
81 #define _REG_LR 33 /* Link Register */
82 #define _REG_PC 34 /* PC (copy of SRR0) */
83 #define _REG_MSR 35 /* MSR (copy of SRR1) */
84 #define _REG_CTR 36 /* Count Register */
85 #define _REG_XER 37 /* Integet Exception Reigster */
86 #define _REG_MQ 38 /* MQ Register (POWER only) */
89 double __fpu_regs
[32]; /* FP0-31 */
90 unsigned int __fpu_fpscr
; /* FP Status and Control Register */
91 unsigned int __fpu_valid
; /* Set together with _UC_FPU */
94 #define _NVR 32 /* Number of Vector registers */
98 unsigned char __vr8
[16];
99 unsigned short __vr16
[8];
100 unsigned int __vr32
[4];
101 } __vrs
[_NVR
] __attribute__((__aligned__(16)));
102 unsigned int __vscr
; /* VSCR */
103 unsigned int __vrsave
; /* VRSAVE */
107 __gregset_t __gregs
; /* General Purpose Register set */
108 __fpregset_t __fpregs
; /* Floating Point Register set */
109 __vrf_t __vrf
; /* Vector Register File */
112 /* Machine-dependent uc_flags */
113 #define _UC_POWERPC_VEC 0x00010000 /* Vector Register File valid */
115 #define _UC_MACHINE_SP(uc) ((uc)->uc_mcontext.__gregs[_REG_R1])
116 #define _UC_MACHINE_PC(uc) ((uc)->uc_mcontext.__gregs[_REG_PC])
117 #define _UC_MACHINE_INTRV(uc) ((uc)->uc_mcontext.__gregs[_REG_R3])
119 #define _UC_MACHINE_SET_PC(uc, pc) _UC_MACHINE_PC(uc) = (pc)
121 #endif /* !_POWERPC_MCONTEXT_H_ */