sys/arch/powerpc/include/psl.h

   1 /*      $NetBSD: psl.h,v 1.13 2005/12/11 12:18:43 christos Exp $        */
   2
   3 /*
   4  * Copyright (C) 1995, 1996 Wolfgang Solfrank.
   5  * Copyright (C) 1995, 1996 TooLs GmbH.
   6  * All rights reserved.
   7  *
   8  * Redistribution and use in source and binary forms, with or without
   9  * modification, are permitted provided that the following conditions
  10  * are met:
  11  * 1. Redistributions of source code must retain the above copyright
  12  *    notice, this list of conditions and the following disclaimer.
  13  * 2. Redistributions in binary form must reproduce the above copyright
  14  *    notice, this list of conditions and the following disclaimer in the
  15  *    documentation and/or other materials provided with the distribution.
  16  * 3. All advertising materials mentioning features or use of this software
  17  *    must display the following acknowledgement:
  18  *      This product includes software developed by TooLs GmbH.
  19  * 4. The name of TooLs GmbH may not be used to endorse or promote products
  20  *    derived from this software without specific prior written permission.
  21  *
  22  * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
  23  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  24  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  25  * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  27  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
  28  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  29  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
  30  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
  31  * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33 #ifndef _POWERPC_PSL_H_
  34 #define _POWERPC_PSL_H_
  35
  36 /*
  37  * Machine State Register (MSR)
  38  *
  39  * The PowerPC 601 does not implement the following bits:
  40  *
  41  *      VEC, POW, ILE, BE, RI, LE[*]
  42  *
  43  * [*] Little-endian mode on the 601 is implemented in the HID0 register.
  44  */
  45 #define PSL_VEC         0x02000000      /* AltiVec vector unit available */
  46 #define PSL_POW         0x00040000      /* power management */
  47 #define PSL_TGPR        0x00020000      /* temp. gpr remapping (mpc603e) */
  48 #define PSL_ILE         0x00010000      /* interrupt endian mode (1 == le) */
  49 #define PSL_EE          0x00008000      /* external interrupt enable */
  50 #define PSL_PR          0x00004000      /* privilege mode (1 == user) */
  51 #define PSL_FP          0x00002000      /* floating point enable */
  52 #define PSL_ME          0x00001000      /* machine check enable */
  53 #define PSL_FE0         0x00000800      /* floating point interrupt mode 0 */
  54 #define PSL_SE          0x00000400      /* single-step trace enable */
  55 #define PSL_BE          0x00000200      /* branch trace enable */
  56 #define PSL_FE1         0x00000100      /* floating point interrupt mode 1 */
  57 #define PSL_IP          0x00000040      /* interrupt prefix */
  58 #define PSL_IR          0x00000020      /* instruction address relocation */
  59 #define PSL_DR          0x00000010      /* data address relocation */
  60 #define PSL_PM          0x00000008      /* Performance monitor marked mode */
  61 #define PSL_RI          0x00000002      /* recoverable interrupt */
  62 #define PSL_LE          0x00000001      /* endian mode (1 == le) */
  63
  64 #define PSL_601_MASK    ~(PSL_VEC|PSL_POW|PSL_ILE|PSL_BE|PSL_RI|PSL_LE)
  65
  66 /* The IBM 970 series does not implemnt LE mode */
  67 #define PSL_970_MASK    ~(PSL_ILE|PSL_LE)
  68
  69 /*
  70  * Floating-point exception modes:
  71  */
  72 #define PSL_FE_DIS      0               /* none */
  73 #define PSL_FE_NONREC   PSL_FE1         /* imprecise non-recoverable */
  74 #define PSL_FE_REC      PSL_FE0         /* imprecise recoverable */
  75 #define PSL_FE_PREC     (PSL_FE0 | PSL_FE1) /* precise */
  76 #define PSL_FE_DFLT     PSL_FE_DIS      /* default == none */
  77
  78 /*
  79  * Note that PSL_POW and PSL_ILE are not in the saved copy of the MSR
  80  */
  81 #define PSL_MBO         0
  82 #define PSL_MBZ         0
  83
  84 /*
  85  * A user is not allowed to change any MSR bits except the following:
  86  * We restrict the test to the low 16 bits of the MSR since those are the
  87  * only ones preserved in the trap.  Note that this means PSL_VEC needs to
  88  * be restored to SRR1 in userret.
  89  */
  90 #if defined(_KERNEL) && !defined(_LOCORE)
  91 #ifdef _KERNEL_OPT
  92 #include "opt_ppcarch.h"
  93 #endif /* _KERNEL_OPT */
  94
  95 #if defined(PPC_OEA) || defined (PPC_OEA64_BRIDGE)
  96 extern int cpu_psluserset, cpu_pslusermod;
  97
  98 #define PSL_USERSET             cpu_psluserset
  99 #define PSL_USERMOD             cpu_pslusermod
 100 #else /* PPC_IBM4XX */
 101 #define PSL_USERSET             (PSL_EE | PSL_PR | PSL_ME | PSL_IR | PSL_DR)
 102 #define PSL_USERMOD             (0)
 103 #endif /* PPC_OEA */
 104
 105 #define PSL_USERSRR1            ((PSL_USERSET|PSL_USERMOD) & 0xFFFF)
 106 #define PSL_USEROK_P(psl)       (((psl) & ~PSL_USERMOD) == PSL_USERSET)
 107 #endif /* !_LOCORE */
 108
 109 #endif  /* _POWERPC_PSL_H_ */