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Expand PMF_FN_* macros.
[netbsd-mini2440.git] / sys / arch / powerpc / oea / cpu_subr.c
blobee5e25a5071d9f834e973e212fa19c39a4ede01c
1 /* $NetBSD: cpu_subr.c,v 1.53 2009/03/18 10:22:34 cegger Exp $ */
2
3 /*-
4 * Copyright (c) 2001 Matt Thomas.
5 * Copyright (c) 2001 Tsubai Masanari.
6 * Copyright (c) 1998, 1999, 2001 Internet Research Institute, Inc.
7 * All rights reserved.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed by
20 * Internet Research Institute, Inc.
21 * 4. The name of the author may not be used to endorse or promote products
22 * derived from this software without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
26 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
27 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
28 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
29 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
30 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
31 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
32 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 */
35
36 #include <sys/cdefs.h>
37 __KERNEL_RCSID(0, "$NetBSD: cpu_subr.c,v 1.53 2009/03/18 10:22:34 cegger Exp $");
38
39 #include "opt_ppcparam.h"
40 #include "opt_multiprocessor.h"
41 #include "opt_altivec.h"
42 #include "sysmon_envsys.h"
43
44 #include <sys/param.h>
45 #include <sys/systm.h>
46 #include <sys/device.h>
47 #include <sys/types.h>
48 #include <sys/lwp.h>
49 #include <sys/malloc.h>
50
51 #include <uvm/uvm_extern.h>
52
53 #include <powerpc/oea/hid.h>
54 #include <powerpc/oea/hid_601.h>
55 #include <powerpc/spr.h>
56 #include <powerpc/oea/cpufeat.h>
57
58 #include <dev/sysmon/sysmonvar.h>
59
60 static void cpu_enable_l2cr(register_t);
61 static void cpu_enable_l3cr(register_t);
62 static void cpu_config_l2cr(int);
63 static void cpu_config_l3cr(int);
64 static void cpu_probe_speed(struct cpu_info *);
65 static void cpu_idlespin(void);
66 #if NSYSMON_ENVSYS > 0
67 static void cpu_tau_setup(struct cpu_info *);
68 static void cpu_tau_refresh(struct sysmon_envsys *, envsys_data_t *);
69 #endif
70
71 int cpu;
72 int ncpus;
73
74 struct fmttab {
75 register_t fmt_mask;
76 register_t fmt_value;
77 const char *fmt_string;
78 };
79
80 /*
81 * This should be one per CPU but since we only support it on 750 variants it
82 * doesn't realy matter since none of them supports SMP
83 */
84 envsys_data_t sensor;
85
86 static const struct fmttab cpu_7450_l2cr_formats[] = {
87 { L2CR_L2E, 0, " disabled" },
88 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" },
89 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" },
90 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" },
91 { L2CR_L2E, ~0, " 256KB L2 cache" },
92 { L2CR_L2PE, 0, " no parity" },
93 { L2CR_L2PE, ~0, " parity enabled" },
94 { 0, 0, NULL }
95 };
96
97 static const struct fmttab cpu_7448_l2cr_formats[] = {
98 { L2CR_L2E, 0, " disabled" },
99 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" },
100 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" },
101 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" },
102 { L2CR_L2E, ~0, " 1MB L2 cache" },
103 { L2CR_L2PE, 0, " no parity" },
104 { L2CR_L2PE, ~0, " parity enabled" },
105 { 0, 0, NULL }
106 };
107
108 static const struct fmttab cpu_7457_l2cr_formats[] = {
109 { L2CR_L2E, 0, " disabled" },
110 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" },
111 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" },
112 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" },
113 { L2CR_L2E, ~0, " 512KB L2 cache" },
114 { L2CR_L2PE, 0, " no parity" },
115 { L2CR_L2PE, ~0, " parity enabled" },
116 { 0, 0, NULL }
117 };
118
119 static const struct fmttab cpu_7450_l3cr_formats[] = {
120 { L3CR_L3DO|L3CR_L3IO, L3CR_L3DO, " data-only" },
121 { L3CR_L3DO|L3CR_L3IO, L3CR_L3IO, " instruction-only" },
122 { L3CR_L3DO|L3CR_L3IO, L3CR_L3DO|L3CR_L3IO, " locked" },
123 { L3CR_L3SIZ, L3SIZ_2M, " 2MB" },
124 { L3CR_L3SIZ, L3SIZ_1M, " 1MB" },
125 { L3CR_L3PE|L3CR_L3APE, L3CR_L3PE|L3CR_L3APE, " parity" },
126 { L3CR_L3PE|L3CR_L3APE, L3CR_L3PE, " data-parity" },
127 { L3CR_L3PE|L3CR_L3APE, L3CR_L3APE, " address-parity" },
128 { L3CR_L3PE|L3CR_L3APE, 0, " no-parity" },
129 { L3CR_L3SIZ, ~0, " L3 cache" },
130 { L3CR_L3RT, L3RT_MSUG2_DDR, " (DDR SRAM)" },
131 { L3CR_L3RT, L3RT_PIPELINE_LATE, " (LW SRAM)" },
132 { L3CR_L3RT, L3RT_PB2_SRAM, " (PB2 SRAM)" },
133 { L3CR_L3CLK, ~0, " at" },
134 { L3CR_L3CLK, L3CLK_20, " 2:1" },
135 { L3CR_L3CLK, L3CLK_25, " 2.5:1" },
136 { L3CR_L3CLK, L3CLK_30, " 3:1" },
137 { L3CR_L3CLK, L3CLK_35, " 3.5:1" },
138 { L3CR_L3CLK, L3CLK_40, " 4:1" },
139 { L3CR_L3CLK, L3CLK_50, " 5:1" },
140 { L3CR_L3CLK, L3CLK_60, " 6:1" },
141 { L3CR_L3CLK, ~0, " ratio" },
142 { 0, 0, NULL },
143 };
144
145 static const struct fmttab cpu_ibm750_l2cr_formats[] = {
146 { L2CR_L2E, 0, " disabled" },
147 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" },
148 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" },
149 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" },
150 { 0, ~0, " 512KB" },
151 { L2CR_L2WT, L2CR_L2WT, " WT" },
152 { L2CR_L2WT, 0, " WB" },
153 { L2CR_L2PE, L2CR_L2PE, " with ECC" },
154 { 0, ~0, " L2 cache" },
155 { 0, 0, NULL }
156 };
157
158 static const struct fmttab cpu_l2cr_formats[] = {
159 { L2CR_L2E, 0, " disabled" },
160 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" },
161 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" },
162 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" },
163 { L2CR_L2PE, L2CR_L2PE, " parity" },
164 { L2CR_L2PE, 0, " no-parity" },
165 { L2CR_L2SIZ, L2SIZ_2M, " 2MB" },
166 { L2CR_L2SIZ, L2SIZ_1M, " 1MB" },
167 { L2CR_L2SIZ, L2SIZ_512K, " 512KB" },
168 { L2CR_L2SIZ, L2SIZ_256K, " 256KB" },
169 { L2CR_L2WT, L2CR_L2WT, " WT" },
170 { L2CR_L2WT, 0, " WB" },
171 { L2CR_L2E, ~0, " L2 cache" },
172 { L2CR_L2RAM, L2RAM_FLOWTHRU_BURST, " (FB SRAM)" },
173 { L2CR_L2RAM, L2RAM_PIPELINE_LATE, " (LW SRAM)" },
174 { L2CR_L2RAM, L2RAM_PIPELINE_BURST, " (PB SRAM)" },
175 { L2CR_L2CLK, ~0, " at" },
176 { L2CR_L2CLK, L2CLK_10, " 1:1" },
177 { L2CR_L2CLK, L2CLK_15, " 1.5:1" },
178 { L2CR_L2CLK, L2CLK_20, " 2:1" },
179 { L2CR_L2CLK, L2CLK_25, " 2.5:1" },
180 { L2CR_L2CLK, L2CLK_30, " 3:1" },
181 { L2CR_L2CLK, L2CLK_35, " 3.5:1" },
182 { L2CR_L2CLK, L2CLK_40, " 4:1" },
183 { L2CR_L2CLK, ~0, " ratio" },
184 { 0, 0, NULL }
185 };
186
187 static void cpu_fmttab_print(const struct fmttab *, register_t);
188
189 struct cputab {
190 const char name[8];
191 uint16_t version;
192 uint16_t revfmt;
193 };
194 #define REVFMT_MAJMIN 1 /* %u.%u */
195 #define REVFMT_HEX 2 /* 0x%04x */
196 #define REVFMT_DEC 3 /* %u */
197 static const struct cputab models[] = {
198 { "601", MPC601, REVFMT_DEC },
199 { "602", MPC602, REVFMT_DEC },
200 { "603", MPC603, REVFMT_MAJMIN },
201 { "603e", MPC603e, REVFMT_MAJMIN },
202 { "603ev", MPC603ev, REVFMT_MAJMIN },
203 { "G2", MPCG2, REVFMT_MAJMIN },
204 { "604", MPC604, REVFMT_MAJMIN },
205 { "604e", MPC604e, REVFMT_MAJMIN },
206 { "604ev", MPC604ev, REVFMT_MAJMIN },
207 { "620", MPC620, REVFMT_HEX },
208 { "750", MPC750, REVFMT_MAJMIN },
209 { "750FX", IBM750FX, REVFMT_MAJMIN },
210 { "7400", MPC7400, REVFMT_MAJMIN },
211 { "7410", MPC7410, REVFMT_MAJMIN },
212 { "7450", MPC7450, REVFMT_MAJMIN },
213 { "7455", MPC7455, REVFMT_MAJMIN },
214 { "7457", MPC7457, REVFMT_MAJMIN },
215 { "7447A", MPC7447A, REVFMT_MAJMIN },
216 { "7448", MPC7448, REVFMT_MAJMIN },
217 { "8240", MPC8240, REVFMT_MAJMIN },
218 { "8245", MPC8245, REVFMT_MAJMIN },
219 { "970", IBM970, REVFMT_MAJMIN },
220 { "970FX", IBM970FX, REVFMT_MAJMIN },
221 { "970MP", IBM970MP, REVFMT_MAJMIN },
222 { "POWER3II", IBMPOWER3II, REVFMT_MAJMIN },
223 { "", 0, REVFMT_HEX }
224 };
225
226 #ifdef MULTIPROCESSOR
227 struct cpu_info cpu_info[CPU_MAXNUM] = { { .ci_curlwp = &lwp0, }, };
228 volatile struct cpu_hatch_data *cpu_hatch_data;
229 volatile int cpu_hatch_stack;
230 extern int ticks_per_intr;
231 #include <powerpc/oea/bat.h>
232 #include <arch/powerpc/pic/picvar.h>
233 #include <arch/powerpc/pic/ipivar.h>
234 extern struct bat battable[];
235 #else
236 struct cpu_info cpu_info[1] = { { .ci_curlwp = &lwp0, }, };
237 #endif /*MULTIPROCESSOR*/
238
239 int cpu_altivec;
240 int cpu_psluserset, cpu_pslusermod;
241 char cpu_model[80];
242
243 /* This is to be called from locore.S, and nowhere else. */
244
245 void
246 cpu_model_init(void)
247 {
248 u_int pvr, vers;
249
250 pvr = mfpvr();
251 vers = pvr >> 16;
252
253 oeacpufeat = 0;
254
255 if ((vers >= IBMRS64II && vers <= IBM970GX) || vers == MPC620 ||
256 vers == IBMCELL || vers == IBMPOWER6P5)
257 oeacpufeat |= OEACPU_64 | OEACPU_64_BRIDGE | OEACPU_NOBAT;
258
259 else if (vers == MPC601)
260 oeacpufeat |= OEACPU_601;
261
262 else if (MPC745X_P(vers) && vers != MPC7450)
263 oeacpufeat |= OEACPU_XBSEN | OEACPU_HIGHBAT | OEACPU_HIGHSPRG;
264 }
265
266 void
267 cpu_fmttab_print(const struct fmttab *fmt, register_t data)
268 {
269 for (; fmt->fmt_mask != 0 || fmt->fmt_value != 0; fmt++) {
270 if ((~fmt->fmt_mask & fmt->fmt_value) != 0 ||
271 (data & fmt->fmt_mask) == fmt->fmt_value)
272 aprint_normal("%s", fmt->fmt_string);
273 }
274 }
275
276 void
277 cpu_idlespin(void)
278 {
279 register_t msr;
280
281 if (powersave <= 0)
282 return;
283
284 __asm volatile(
285 "sync;"
286 "mfmsr %0;"
287 "oris %0,%0,%1@h;" /* enter power saving mode */
288 "mtmsr %0;"
289 "isync;"
290 : "=r"(msr)
291 : "J"(PSL_POW));
292 }
293
294 void
295 cpu_probe_cache(void)
296 {
297 u_int assoc, pvr, vers;
298
299 pvr = mfpvr();
300 vers = pvr >> 16;
301
302
303 /* Presently common across almost all implementations. */
304 curcpu()->ci_ci.dcache_line_size = 32;
305 curcpu()->ci_ci.icache_line_size = 32;
306
307
308 switch (vers) {
309 #define K *1024
310 case IBM750FX:
311 case MPC601:
312 case MPC750:
313 case MPC7400:
314 case MPC7447A:
315 case MPC7448:
316 case MPC7450:
317 case MPC7455:
318 case MPC7457:
319 curcpu()->ci_ci.dcache_size = 32 K;
320 curcpu()->ci_ci.icache_size = 32 K;
321 assoc = 8;
322 break;
323 case MPC603:
324 curcpu()->ci_ci.dcache_size = 8 K;
325 curcpu()->ci_ci.icache_size = 8 K;
326 assoc = 2;
327 break;
328 case MPC603e:
329 case MPC603ev:
330 case MPC604:
331 case MPC8240:
332 case MPC8245:
333 case MPCG2:
334 curcpu()->ci_ci.dcache_size = 16 K;
335 curcpu()->ci_ci.icache_size = 16 K;
336 assoc = 4;
337 break;
338 case MPC604e:
339 case MPC604ev:
340 curcpu()->ci_ci.dcache_size = 32 K;
341 curcpu()->ci_ci.icache_size = 32 K;
342 assoc = 4;
343 break;
344 case IBMPOWER3II:
345 curcpu()->ci_ci.dcache_size = 64 K;
346 curcpu()->ci_ci.icache_size = 32 K;
347 curcpu()->ci_ci.dcache_line_size = 128;
348 curcpu()->ci_ci.icache_line_size = 128;
349 assoc = 128; /* not a typo */
350 break;
351 case IBM970:
352 case IBM970FX:
353 case IBM970MP:
354 curcpu()->ci_ci.dcache_size = 32 K;
355 curcpu()->ci_ci.icache_size = 64 K;
356 curcpu()->ci_ci.dcache_line_size = 128;
357 curcpu()->ci_ci.icache_line_size = 128;
358 assoc = 2;
359 break;
360
361 default:
362 curcpu()->ci_ci.dcache_size = PAGE_SIZE;
363 curcpu()->ci_ci.icache_size = PAGE_SIZE;
364 assoc = 1;
365 #undef K
366 }
367
368 /*
369 * Possibly recolor.
370 */
371 uvm_page_recolor(atop(curcpu()->ci_ci.dcache_size / assoc));
372 }
373
374 struct cpu_info *
375 cpu_attach_common(struct device *self, int id)
376 {
377 struct cpu_info *ci;
378 u_int pvr, vers;
379
380 ci = &cpu_info[id];
381 #ifndef MULTIPROCESSOR
382 /*
383 * If this isn't the primary CPU, print an error message
384 * and just bail out.
385 */
386 if (id != 0) {
387 aprint_normal(": ID %d\n", id);
388 aprint_normal("%s: processor off-line; multiprocessor support "
389 "not present in kernel\n", self->dv_xname);
390 return (NULL);
391 }
392 #endif
393
394 ci->ci_cpuid = id;
395 ci->ci_intrdepth = -1;
396 ci->ci_dev = self;
397 ci->ci_idlespin = cpu_idlespin;
398
399 pvr = mfpvr();
400 vers = (pvr >> 16) & 0xffff;
401
402 switch (id) {
403 case 0:
404 /* load my cpu_number to PIR */
405 switch (vers) {
406 case MPC601:
407 case MPC604:
408 case MPC604e:
409 case MPC604ev:
410 case MPC7400:
411 case MPC7410:
412 case MPC7447A:
413 case MPC7448:
414 case MPC7450:
415 case MPC7455:
416 case MPC7457:
417 mtspr(SPR_PIR, id);
418 }
419 cpu_setup(self, ci);
420 break;
421 default:
422 if (id >= CPU_MAXNUM) {
423 aprint_normal(": more than %d cpus?\n", CPU_MAXNUM);
424 panic("cpuattach");
425 }
426 #ifndef MULTIPROCESSOR
427 aprint_normal(" not configured\n");
428 return NULL;
429 #else
430 mi_cpu_attach(ci);
431 break;
432 #endif
433 }
434 return (ci);
435 }
436
437 void
438 cpu_setup(struct device *self, struct cpu_info *ci)
439 {
440 u_int hid0, hid0_save, pvr, vers;
441 const char *bitmask;
442 char hidbuf[128];
443 char model[80];
444
445 pvr = mfpvr();
446 vers = (pvr >> 16) & 0xffff;
447
448 cpu_identify(model, sizeof(model));
449 aprint_normal(": %s, ID %d%s\n", model, cpu_number(),
450 cpu_number() == 0 ? " (primary)" : "");
451
452 /* set the cpu number */
453 ci->ci_cpuid = cpu_number();
454 hid0_save = hid0 = mfspr(SPR_HID0);
455
456 cpu_probe_cache();
457
458 /*
459 * Configure power-saving mode.
460 */
461 switch (vers) {
462 case MPC604:
463 case MPC604e:
464 case MPC604ev:
465 /*
466 * Do not have HID0 support settings, but can support
467 * MSR[POW] off
468 */
469 powersave = 1;
470 break;
471
472 case MPC603:
473 case MPC603e:
474 case MPC603ev:
475 case MPC750:
476 case IBM750FX:
477 case MPC7400:
478 case MPC7410:
479 case MPC8240:
480 case MPC8245:
481 case MPCG2:
482 /* Select DOZE mode. */
483 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP);
484 hid0 |= HID0_DOZE | HID0_DPM;
485 powersave = 1;
486 break;
487
488 case MPC7447A:
489 case MPC7448:
490 case MPC7457:
491 case MPC7455:
492 case MPC7450:
493 /* Enable the 7450 branch caches */
494 hid0 |= HID0_SGE | HID0_BTIC;
495 hid0 |= HID0_LRSTK | HID0_FOLD | HID0_BHT;
496 /* Enable more and larger BAT registers */
497 if (oeacpufeat & OEACPU_XBSEN)
498 hid0 |= HID0_XBSEN;
499 if (oeacpufeat & OEACPU_HIGHBAT)
500 hid0 |= HID0_HIGH_BAT_EN;
501 /* Disable BTIC on 7450 Rev 2.0 or earlier */
502 if (vers == MPC7450 && (pvr & 0xFFFF) <= 0x0200)
503 hid0 &= ~HID0_BTIC;
504 /* Select NAP mode. */
505 hid0 &= ~HID0_SLEEP;
506 hid0 |= HID0_NAP | HID0_DPM;
507 powersave = 1;
508 break;
509
510 case IBM970:
511 case IBM970FX:
512 case IBM970MP:
513 case IBMPOWER3II:
514 default:
515 /* No power-saving mode is available. */ ;
516 }
517
518 #ifdef NAPMODE
519 switch (vers) {
520 case IBM750FX:
521 case MPC750:
522 case MPC7400:
523 /* Select NAP mode. */
524 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP);
525 hid0 |= HID0_NAP;
526 break;
527 }
528 #endif
529
530 switch (vers) {
531 case IBM750FX:
532 case MPC750:
533 hid0 &= ~HID0_DBP; /* XXX correct? */
534 hid0 |= HID0_EMCP | HID0_BTIC | HID0_SGE | HID0_BHT;
535 break;
536
537 case MPC7400:
538 case MPC7410:
539 hid0 &= ~HID0_SPD;
540 hid0 |= HID0_EMCP | HID0_BTIC | HID0_SGE | HID0_BHT;
541 hid0 |= HID0_EIEC;
542 break;
543 }
544
545 if (hid0 != hid0_save) {
546 mtspr(SPR_HID0, hid0);
547 __asm volatile("sync;isync");
548 }
549
550
551 switch (vers) {
552 case MPC601:
553 bitmask = HID0_601_BITMASK;
554 break;
555 case MPC7450:
556 case MPC7455:
557 case MPC7457:
558 bitmask = HID0_7450_BITMASK;
559 break;
560 case IBM970:
561 case IBM970FX:
562 case IBM970MP:
563 bitmask = 0;
564 break;
565 default:
566 bitmask = HID0_BITMASK;
567 break;
568 }
569 snprintb(hidbuf, sizeof hidbuf, bitmask, hid0);
570 aprint_normal("%s: HID0 %s, powersave: %d\n", self->dv_xname, hidbuf,
571 powersave);
572
573 ci->ci_khz = 0;
574
575 /*
576 * Display speed and cache configuration.
577 */
578 switch (vers) {
579 case MPC604:
580 case MPC604e:
581 case MPC604ev:
582 case MPC750:
583 case IBM750FX:
584 case MPC7400:
585 case MPC7410:
586 case MPC7447A:
587 case MPC7448:
588 case MPC7450:
589 case MPC7455:
590 case MPC7457:
591 aprint_normal("%s: ", self->dv_xname);
592 cpu_probe_speed(ci);
593 aprint_normal("%u.%02u MHz",
594 ci->ci_khz / 1000, (ci->ci_khz / 10) % 100);
595 switch (vers) {
596 case MPC7450: /* 7441 does not have L3! */
597 case MPC7455: /* 7445 does not have L3! */
598 case MPC7457: /* 7447 does not have L3! */
599 cpu_config_l3cr(vers);
600 break;
601 case IBM750FX:
602 case MPC750:
603 case MPC7400:
604 case MPC7410:
605 case MPC7447A:
606 case MPC7448:
607 cpu_config_l2cr(pvr);
608 break;
609 default:
610 break;
611 }
612 aprint_normal("\n");
613 break;
614 }
615
616 #if NSYSMON_ENVSYS > 0
617 /*
618 * Attach MPC750 temperature sensor to the envsys subsystem.
619 * XXX the 74xx series also has this sensor, but it is not
620 * XXX supported by Motorola and may return values that are off by
621 * XXX 35-55 degrees C.
622 */
623 if (vers == MPC750 || vers == IBM750FX)
624 cpu_tau_setup(ci);
625 #endif
626
627 evcnt_attach_dynamic(&ci->ci_ev_clock, EVCNT_TYPE_INTR,
628 NULL, self->dv_xname, "clock");
629 evcnt_attach_dynamic(&ci->ci_ev_softclock, EVCNT_TYPE_INTR,
630 NULL, self->dv_xname, "soft clock");
631 evcnt_attach_dynamic(&ci->ci_ev_softnet, EVCNT_TYPE_INTR,
632 NULL, self->dv_xname, "soft net");
633 evcnt_attach_dynamic(&ci->ci_ev_softserial, EVCNT_TYPE_INTR,
634 NULL, self->dv_xname, "soft serial");
635 evcnt_attach_dynamic(&ci->ci_ev_traps, EVCNT_TYPE_TRAP,
636 NULL, self->dv_xname, "traps");
637 evcnt_attach_dynamic(&ci->ci_ev_kdsi, EVCNT_TYPE_TRAP,
638 &ci->ci_ev_traps, self->dv_xname, "kernel DSI traps");
639 evcnt_attach_dynamic(&ci->ci_ev_udsi, EVCNT_TYPE_TRAP,
640 &ci->ci_ev_traps, self->dv_xname, "user DSI traps");
641 evcnt_attach_dynamic(&ci->ci_ev_udsi_fatal, EVCNT_TYPE_TRAP,
642 &ci->ci_ev_udsi, self->dv_xname, "user DSI failures");
643 evcnt_attach_dynamic(&ci->ci_ev_kisi, EVCNT_TYPE_TRAP,
644 &ci->ci_ev_traps, self->dv_xname, "kernel ISI traps");
645 evcnt_attach_dynamic(&ci->ci_ev_isi, EVCNT_TYPE_TRAP,
646 &ci->ci_ev_traps, self->dv_xname, "user ISI traps");
647 evcnt_attach_dynamic(&ci->ci_ev_isi_fatal, EVCNT_TYPE_TRAP,
648 &ci->ci_ev_isi, self->dv_xname, "user ISI failures");
649 evcnt_attach_dynamic(&ci->ci_ev_scalls, EVCNT_TYPE_TRAP,
650 &ci->ci_ev_traps, self->dv_xname, "system call traps");
651 evcnt_attach_dynamic(&ci->ci_ev_pgm, EVCNT_TYPE_TRAP,
652 &ci->ci_ev_traps, self->dv_xname, "PGM traps");
653 evcnt_attach_dynamic(&ci->ci_ev_fpu, EVCNT_TYPE_TRAP,
654 &ci->ci_ev_traps, self->dv_xname, "FPU unavailable traps");
655 evcnt_attach_dynamic(&ci->ci_ev_fpusw, EVCNT_TYPE_TRAP,
656 &ci->ci_ev_fpu, self->dv_xname, "FPU context switches");
657 evcnt_attach_dynamic(&ci->ci_ev_ali, EVCNT_TYPE_TRAP,
658 &ci->ci_ev_traps, self->dv_xname, "user alignment traps");
659 evcnt_attach_dynamic(&ci->ci_ev_ali_fatal, EVCNT_TYPE_TRAP,
660 &ci->ci_ev_ali, self->dv_xname, "user alignment traps");
661 evcnt_attach_dynamic(&ci->ci_ev_umchk, EVCNT_TYPE_TRAP,
662 &ci->ci_ev_umchk, self->dv_xname, "user MCHK failures");
663 evcnt_attach_dynamic(&ci->ci_ev_vec, EVCNT_TYPE_TRAP,
664 &ci->ci_ev_traps, self->dv_xname, "AltiVec unavailable");
665 #ifdef ALTIVEC
666 if (cpu_altivec) {
667 evcnt_attach_dynamic(&ci->ci_ev_vecsw, EVCNT_TYPE_TRAP,
668 &ci->ci_ev_vec, self->dv_xname, "AltiVec context switches");
669 }
670 #endif
671 evcnt_attach_dynamic(&ci->ci_ev_ipi, EVCNT_TYPE_INTR,
672 NULL, self->dv_xname, "IPIs");
673 }
674
675 /*
676 * According to a document labeled "PVR Register Settings":
677 ** For integrated microprocessors the PVR register inside the device
678 ** will identify the version of the microprocessor core. You must also
679 ** read the Device ID, PCI register 02, to identify the part and the
680 ** Revision ID, PCI register 08, to identify the revision of the
681 ** integrated microprocessor.
682 * This apparently applies to 8240/8245/8241, PVR 00810101 and 80811014
683 */
684
685 void
686 cpu_identify(char *str, size_t len)
687 {
688 u_int pvr, major, minor;
689 uint16_t vers, rev, revfmt;
690 const struct cputab *cp;
691 const char *name;
692 size_t n;
693
694 pvr = mfpvr();
695 vers = pvr >> 16;
696 rev = pvr;
697
698 switch (vers) {
699 case MPC7410:
700 minor = (pvr >> 0) & 0xff;
701 major = minor <= 4 ? 1 : 2;
702 break;
703 case MPCG2: /*XXX see note above */
704 major = (pvr >> 4) & 0xf;
705 minor = (pvr >> 0) & 0xf;
706 break;
707 default:
708 major = (pvr >> 8) & 0xf;
709 minor = (pvr >> 0) & 0xf;
710 }
711
712 for (cp = models; cp->name[0] != '\0'; cp++) {
713 if (cp->version == vers)
714 break;
715 }
716
717 if (str == NULL) {
718 str = cpu_model;
719 len = sizeof(cpu_model);
720 cpu = vers;
721 }
722
723 revfmt = cp->revfmt;
724 name = cp->name;
725 if (rev == MPC750 && pvr == 15) {
726 name = "755";
727 revfmt = REVFMT_HEX;
728 }
729
730 if (cp->name[0] != '\0') {
731 n = snprintf(str, len, "%s (Revision ", cp->name);
732 } else {
733 n = snprintf(str, len, "Version %#x (Revision ", vers);
734 }
735 if (len > n) {
736 switch (revfmt) {
737 case REVFMT_MAJMIN:
738 snprintf(str + n, len - n, "%u.%u)", major, minor);
739 break;
740 case REVFMT_HEX:
741 snprintf(str + n, len - n, "0x%04x)", rev);
742 break;
743 case REVFMT_DEC:
744 snprintf(str + n, len - n, "%u)", rev);
745 break;
746 }
747 }
748 }
749
750 #ifdef L2CR_CONFIG
751 u_int l2cr_config = L2CR_CONFIG;
752 #else
753 u_int l2cr_config = 0;
754 #endif
755
756 #ifdef L3CR_CONFIG
757 u_int l3cr_config = L3CR_CONFIG;
758 #else
759 u_int l3cr_config = 0;
760 #endif
761
762 void
763 cpu_enable_l2cr(register_t l2cr)
764 {
765 register_t msr, x;
766 uint16_t vers;
767
768 vers = mfpvr() >> 16;
769
770 /* Disable interrupts and set the cache config bits. */
771 msr = mfmsr();
772 mtmsr(msr & ~PSL_EE);
773 #ifdef ALTIVEC
774 if (cpu_altivec)
775 __asm volatile("dssall");
776 #endif
777 __asm volatile("sync");
778 mtspr(SPR_L2CR, l2cr & ~L2CR_L2E);
779 __asm volatile("sync");
780
781 /* Wait for L2 clock to be stable (640 L2 clocks). */
782 delay(100);
783
784 /* Invalidate all L2 contents. */
785 if (MPC745X_P(vers)) {
786 mtspr(SPR_L2CR, l2cr | L2CR_L2I);
787 do {
788 x = mfspr(SPR_L2CR);
789 } while (x & L2CR_L2I);
790 } else {
791 mtspr(SPR_L2CR, l2cr | L2CR_L2I);
792 do {
793 x = mfspr(SPR_L2CR);
794 } while (x & L2CR_L2IP);
795 }
796 /* Enable L2 cache. */
797 l2cr |= L2CR_L2E;
798 mtspr(SPR_L2CR, l2cr);
799 mtmsr(msr);
800 }
801
802 void
803 cpu_enable_l3cr(register_t l3cr)
804 {
805 register_t x;
806
807 /* By The Book (numbered steps from section 3.7.1.3 of MPC7450UM) */
808
809 /*
810 * 1: Set all L3CR bits for final config except L3E, L3I, L3PE, and
811 * L3CLKEN. (also mask off reserved bits in case they were included
812 * in L3CR_CONFIG)
813 */
814 l3cr &= ~(L3CR_L3E|L3CR_L3I|L3CR_L3PE|L3CR_L3CLKEN|L3CR_RESERVED);
815 mtspr(SPR_L3CR, l3cr);
816
817 /* 2: Set L3CR[5] (otherwise reserved bit) to 1 */
818 l3cr |= 0x04000000;
819 mtspr(SPR_L3CR, l3cr);
820
821 /* 3: Set L3CLKEN to 1*/
822 l3cr |= L3CR_L3CLKEN;
823 mtspr(SPR_L3CR, l3cr);
824
825 /* 4/5: Perform a global cache invalidate (ref section 3.7.3.6) */
826 __asm volatile("dssall;sync");
827 /* L3 cache is already disabled, no need to clear L3E */
828 mtspr(SPR_L3CR, l3cr|L3CR_L3I);
829 do {
830 x = mfspr(SPR_L3CR);
831 } while (x & L3CR_L3I);
832
833 /* 6: Clear L3CLKEN to 0 */
834 l3cr &= ~L3CR_L3CLKEN;
835 mtspr(SPR_L3CR, l3cr);
836
837 /* 7: Perform a 'sync' and wait at least 100 CPU cycles */
838 __asm volatile("sync");
839 delay(100);
840
841 /* 8: Set L3E and L3CLKEN */
842 l3cr |= (L3CR_L3E|L3CR_L3CLKEN);
843 mtspr(SPR_L3CR, l3cr);
844
845 /* 9: Perform a 'sync' and wait at least 100 CPU cycles */
846 __asm volatile("sync");
847 delay(100);
848 }
849
850 void
851 cpu_config_l2cr(int pvr)
852 {
853 register_t l2cr;
854 u_int vers = (pvr >> 16) & 0xffff;
855
856 l2cr = mfspr(SPR_L2CR);
857
858 /*
859 * For MP systems, the firmware may only configure the L2 cache
860 * on the first CPU. In this case, assume that the other CPUs
861 * should use the same value for L2CR.
862 */
863 if ((l2cr & L2CR_L2E) != 0 && l2cr_config == 0) {
864 l2cr_config = l2cr;
865 }
866
867 /*
868 * Configure L2 cache if not enabled.
869 */
870 if ((l2cr & L2CR_L2E) == 0 && l2cr_config != 0) {
871 cpu_enable_l2cr(l2cr_config);
872 l2cr = mfspr(SPR_L2CR);
873 }
874
875 if ((l2cr & L2CR_L2E) == 0) {
876 aprint_normal(" L2 cache present but not enabled ");
877 return;
878 }
879 aprint_normal(",");
880
881 switch (vers) {
882 case IBM750FX:
883 cpu_fmttab_print(cpu_ibm750_l2cr_formats, l2cr);
884 break;
885 case MPC750:
886 if ((pvr & 0xffffff00) == 0x00082200 /* IBM750CX */ ||
887 (pvr & 0xffffef00) == 0x00082300 /* IBM750CXe */)
888 cpu_fmttab_print(cpu_ibm750_l2cr_formats, l2cr);
889 else
890 cpu_fmttab_print(cpu_l2cr_formats, l2cr);
891 break;
892 case MPC7447A:
893 case MPC7457:
894 cpu_fmttab_print(cpu_7457_l2cr_formats, l2cr);
895 return;
896 case MPC7448:
897 cpu_fmttab_print(cpu_7448_l2cr_formats, l2cr);
898 return;
899 case MPC7450:
900 case MPC7455:
901 cpu_fmttab_print(cpu_7450_l2cr_formats, l2cr);
902 break;
903 default:
904 cpu_fmttab_print(cpu_l2cr_formats, l2cr);
905 break;
906 }
907 }
908
909 void
910 cpu_config_l3cr(int vers)
911 {
912 register_t l2cr;
913 register_t l3cr;
914
915 l2cr = mfspr(SPR_L2CR);
916
917 /*
918 * For MP systems, the firmware may only configure the L2 cache
919 * on the first CPU. In this case, assume that the other CPUs
920 * should use the same value for L2CR.
921 */
922 if ((l2cr & L2CR_L2E) != 0 && l2cr_config == 0) {
923 l2cr_config = l2cr;
924 }
925
926 /*
927 * Configure L2 cache if not enabled.
928 */
929 if ((l2cr & L2CR_L2E) == 0 && l2cr_config != 0) {
930 cpu_enable_l2cr(l2cr_config);
931 l2cr = mfspr(SPR_L2CR);
932 }
933
934 aprint_normal(",");
935 switch (vers) {
936 case MPC7447A:
937 case MPC7457:
938 cpu_fmttab_print(cpu_7457_l2cr_formats, l2cr);
939 return;
940 case MPC7448:
941 cpu_fmttab_print(cpu_7448_l2cr_formats, l2cr);
942 return;
943 default:
944 cpu_fmttab_print(cpu_7450_l2cr_formats, l2cr);
945 break;
946 }
947
948 l3cr = mfspr(SPR_L3CR);
949
950 /*
951 * For MP systems, the firmware may only configure the L3 cache
952 * on the first CPU. In this case, assume that the other CPUs
953 * should use the same value for L3CR.
954 */
955 if ((l3cr & L3CR_L3E) != 0 && l3cr_config == 0) {
956 l3cr_config = l3cr;
957 }
958
959 /*
960 * Configure L3 cache if not enabled.
961 */
962 if ((l3cr & L3CR_L3E) == 0 && l3cr_config != 0) {
963 cpu_enable_l3cr(l3cr_config);
964 l3cr = mfspr(SPR_L3CR);
965 }
966
967 if (l3cr & L3CR_L3E) {
968 aprint_normal(",");
969 cpu_fmttab_print(cpu_7450_l3cr_formats, l3cr);
970 }
971 }
972
973 void
974 cpu_probe_speed(struct cpu_info *ci)
975 {
976 uint64_t cps;
977
978 mtspr(SPR_MMCR0, MMCR0_FC);
979 mtspr(SPR_PMC1, 0);
980 mtspr(SPR_MMCR0, MMCR0_PMC1SEL(PMCN_CYCLES));
981 delay(100000);
982 cps = (mfspr(SPR_PMC1) * 10) + 4999;
983
984 mtspr(SPR_MMCR0, MMCR0_FC);
985
986 ci->ci_khz = cps / 1000;
987 }
988
989 #if NSYSMON_ENVSYS > 0
990 void
991 cpu_tau_setup(struct cpu_info *ci)
992 {
993 struct sysmon_envsys *sme;
994 int error, therm_delay;
995
996 mtspr(SPR_THRM1, SPR_THRM_VALID);
997 mtspr(SPR_THRM2, 0);
998
999 /*
1000 * we need to figure out how much 20+us in units of CPU clock cycles
1001 * are
1002 */
1003
1004 therm_delay = ci->ci_khz / 40; /* 25us just to be safe */
1005
1006 mtspr(SPR_THRM3, SPR_THRM_TIMER(therm_delay) | SPR_THRM_ENABLE);
1007
1008 sme = sysmon_envsys_create();
1009
1010 sensor.units = ENVSYS_STEMP;
1011 (void)strlcpy(sensor.desc, "CPU Temp", sizeof(sensor.desc));
1012 if (sysmon_envsys_sensor_attach(sme, &sensor)) {
1013 sysmon_envsys_destroy(sme);
1014 return;
1015 }
1016
1017 sme->sme_name = ci->ci_dev->dv_xname;
1018 sme->sme_cookie = ci;
1019 sme->sme_refresh = cpu_tau_refresh;
1020
1021 if ((error = sysmon_envsys_register(sme)) != 0) {
1022 aprint_error("%s: unable to register with sysmon (%d)\n",
1023 ci->ci_dev->dv_xname, error);
1024 sysmon_envsys_destroy(sme);
1025 }
1026 }
1027
1028
1029 /* Find the temperature of the CPU. */
1030 void
1031 cpu_tau_refresh(struct sysmon_envsys *sme, envsys_data_t *edata)
1032 {
1033 int i, threshold, count;
1034
1035 threshold = 64; /* Half of the 7-bit sensor range */
1036
1037 /* Successive-approximation code adapted from Motorola
1038 * application note AN1800/D, "Programming the Thermal Assist
1039 * Unit in the MPC750 Microprocessor".
1040 */
1041 for (i = 5; i >= 0 ; i--) {
1042 mtspr(SPR_THRM1,
1043 SPR_THRM_THRESHOLD(threshold) | SPR_THRM_VALID);
1044 count = 0;
1045 while ((count < 100000) &&
1046 ((mfspr(SPR_THRM1) & SPR_THRM_TIV) == 0)) {
1047 count++;
1048 delay(1);
1049 }
1050 if (mfspr(SPR_THRM1) & SPR_THRM_TIN) {
1051 /* The interrupt bit was set, meaning the
1052 * temperature was above the threshold
1053 */
1054 threshold += 1 << i;
1055 } else {
1056 /* Temperature was below the threshold */
1057 threshold -= 1 << i;
1058 }
1059
1060 }
1061 threshold += 2;
1062
1063 /* Convert the temperature in degrees C to microkelvin */
1064 edata->value_cur = (threshold * 1000000) + 273150000;
1065 edata->state = ENVSYS_SVALID;
1066 }
1067 #endif /* NSYSMON_ENVSYS > 0 */
1068
1069 #ifdef MULTIPROCESSOR
1070 extern volatile u_int cpu_spinstart_ack;
1071
1072 int
1073 cpu_spinup(struct device *self, struct cpu_info *ci)
1074 {
1075 volatile struct cpu_hatch_data hatch_data, *h = &hatch_data;
1076 struct pglist mlist;
1077 int i, error, pvr, vers;
1078 char *cp, *hp;
1079
1080 pvr = mfpvr();
1081 vers = pvr >> 16;
1082 KASSERT(ci != curcpu());
1083
1084 /*
1085 * Allocate some contiguous pages for the intteup PCB and stack
1086 * from the lowest 256MB (because bat0 always maps it va == pa).
1087 * Must be 16 byte aligned.
1088 */
1089 error = uvm_pglistalloc(INTSTK, 0x10000, 0x10000000, 16, 0,
1090 &mlist, 1, 1);
1091 if (error) {
1092 aprint_error(": unable to allocate idle stack\n");
1093 return -1;
1094 }
1095
1096 KASSERT(ci != &cpu_info[0]);
1097
1098 cp = (void *)VM_PAGE_TO_PHYS(TAILQ_FIRST(&mlist));
1099 memset(cp, 0, INTSTK);
1100
1101 ci->ci_intstk = cp;
1102
1103 /* Now allocate a hatch stack */
1104 error = uvm_pglistalloc(0x1000, 0x10000, 0x10000000, 16, 0,
1105 &mlist, 1, 1);
1106 if (error) {
1107 aprint_error(": unable to allocate hatch stack\n");
1108 return -1;
1109 }
1110
1111 hp = (void *)VM_PAGE_TO_PHYS(TAILQ_FIRST(&mlist));
1112 memset(hp, 0, 0x1000);
1113
1114 /* Initialize secondary cpu's initial lwp to its idlelwp. */
1115 ci->ci_curlwp = ci->ci_data.cpu_idlelwp;
1116 ci->ci_curpcb = lwp_getpcb(ci->ci_curlwp);
1117 ci->ci_curpm = ci->ci_curpcb->pcb_pm;
1118
1119 cpu_hatch_data = h;
1120 h->running = 0;
1121 h->self = self;
1122 h->ci = ci;
1123 h->pir = ci->ci_cpuid;
1124
1125 cpu_hatch_stack = (uint32_t)hp;
1126 ci->ci_lasttb = cpu_info[0].ci_lasttb;
1127
1128 /* copy special registers */
1129
1130 h->hid0 = mfspr(SPR_HID0);
1131
1132 __asm volatile ("mfsdr1 %0" : "=r"(h->sdr1));
1133 for (i = 0; i < 16; i++) {
1134 __asm ("mfsrin %0,%1" : "=r"(h->sr[i]) :
1135 "r"(i << ADDR_SR_SHFT));
1136 }
1137 if (oeacpufeat & OEACPU_64)
1138 h->asr = mfspr(SPR_ASR);
1139 else
1140 h->asr = 0;
1141
1142 /* copy the bat regs */
1143 __asm volatile ("mfibatu %0,0" : "=r"(h->batu[0]));
1144 __asm volatile ("mfibatl %0,0" : "=r"(h->batl[0]));
1145 __asm volatile ("mfibatu %0,1" : "=r"(h->batu[1]));
1146 __asm volatile ("mfibatl %0,1" : "=r"(h->batl[1]));
1147 __asm volatile ("mfibatu %0,2" : "=r"(h->batu[2]));
1148 __asm volatile ("mfibatl %0,2" : "=r"(h->batl[2]));
1149 __asm volatile ("mfibatu %0,3" : "=r"(h->batu[3]));
1150 __asm volatile ("mfibatl %0,3" : "=r"(h->batl[3]));
1151 __asm volatile ("sync; isync");
1152
1153 if (md_setup_trampoline(h, ci) == -1)
1154 return -1;
1155 md_presync_timebase(h);
1156 md_start_timebase(h);
1157
1158 /* wait for secondary printf */
1159
1160 delay(200000);
1161
1162 if (h->running < 1) {
1163 aprint_error("%d:CPU %d didn't start %d\n", cpu_spinstart_ack,
1164 ci->ci_cpuid, cpu_spinstart_ack);
1165 Debugger();
1166 return -1;
1167 }
1168
1169 /* Register IPI Interrupt */
1170 if (ipiops.ppc_establish_ipi)
1171 ipiops.ppc_establish_ipi(IST_LEVEL, IPL_HIGH, NULL);
1172
1173 return 0;
1174 }
1175
1176 static volatile int start_secondary_cpu;
1177 extern void tlbia(void);
1178
1179 register_t
1180 cpu_hatch(void)
1181 {
1182 volatile struct cpu_hatch_data *h = cpu_hatch_data;
1183 struct cpu_info * const ci = h->ci;
1184 struct pcb *pcb;
1185 u_int msr;
1186 int i;
1187
1188 /* Initialize timebase. */
1189 __asm ("mttbl %0; mttbu %0; mttbl %0" :: "r"(0));
1190
1191 /*
1192 * Set PIR (Processor Identification Register). i.e. whoami
1193 * Note that PIR is read-only on some CPU versions, so we write to it
1194 * only if it has a different value than we need.
1195 */
1196
1197 msr = mfspr(SPR_PIR);
1198 if (msr != h->pir)
1199 mtspr(SPR_PIR, h->pir);
1200
1201 __asm volatile ("mtsprg 0,%0" :: "r"(ci));
1202 cpu_spinstart_ack = 0;
1203
1204 /* Initialize MMU. */
1205 __asm ("mtibatu 0,%0" :: "r"(h->batu[0]));
1206 __asm ("mtibatl 0,%0" :: "r"(h->batl[0]));
1207 __asm ("mtibatu 1,%0" :: "r"(h->batu[1]));
1208 __asm ("mtibatl 1,%0" :: "r"(h->batl[1]));
1209 __asm ("mtibatu 2,%0" :: "r"(h->batu[2]));
1210 __asm ("mtibatl 2,%0" :: "r"(h->batl[2]));
1211 __asm ("mtibatu 3,%0" :: "r"(h->batu[3]));
1212 __asm ("mtibatl 3,%0" :: "r"(h->batl[3]));
1213
1214 mtspr(SPR_HID0, h->hid0);
1215
1216 __asm ("mtibatl 0,%0; mtibatu 0,%1; mtdbatl 0,%0; mtdbatu 0,%1;"
1217 :: "r"(battable[0].batl), "r"(battable[0].batu));
1218
1219 __asm volatile ("sync");
1220 for (i = 0; i < 16; i++)
1221 __asm ("mtsrin %0,%1" :: "r"(h->sr[i]), "r"(i << ADDR_SR_SHFT));
1222 __asm volatile ("sync; isync");
1223
1224 if (oeacpufeat & OEACPU_64)
1225 mtspr(SPR_ASR, h->asr);
1226
1227 cpu_spinstart_ack = 1;
1228 __asm ("ptesync");
1229 __asm ("mtsdr1 %0" :: "r"(h->sdr1));
1230 __asm volatile ("sync; isync");
1231
1232 cpu_spinstart_ack = 5;
1233 for (i = 0; i < 16; i++)
1234 __asm ("mfsrin %0,%1" : "=r"(h->sr[i]) :
1235 "r"(i << ADDR_SR_SHFT));
1236
1237 /* Enable I/D address translations. */
1238 msr = mfmsr();
1239 msr |= PSL_IR|PSL_DR|PSL_ME|PSL_RI;
1240 mtmsr(msr);
1241 __asm volatile ("sync; isync");
1242 cpu_spinstart_ack = 2;
1243
1244 md_sync_timebase(h);
1245
1246 cpu_setup(h->self, ci);
1247
1248 h->running = 1;
1249 __asm volatile ("sync; isync");
1250
1251 while (start_secondary_cpu == 0)
1252 ;
1253
1254 __asm volatile ("sync; isync");
1255
1256 aprint_normal("cpu%d started\n", curcpu()->ci_index);
1257 __asm volatile ("mtdec %0" :: "r"(ticks_per_intr));
1258
1259 md_setup_interrupts();
1260
1261 ci->ci_ipending = 0;
1262 ci->ci_cpl = 0;
1263
1264 mtmsr(mfmsr() | PSL_EE);
1265 pcb = lwp_getpcb(ci->ci_data.cpu_idlelwp);
1266 return pcb->pcb_sp;
1267 }
1268
1269 void
1270 cpu_boot_secondary_processors(void)
1271 {
1272 start_secondary_cpu = 1;
1273 __asm volatile ("sync");
1274 }
1275
1276 #endif /*MULTIPROCESSOR*/
NetBSD on the FriendlyARM MINI2440