1 /* $NetBSD: dp8573areg.h,v 1.2 2005/12/11 12:18:53 christos Exp $ */
4 * Copyright (c) 2003 Steve Rumble
5 * Copyright (c) 2001 Erik Reid
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 #ifndef _DEV_IC_DP8573AREG_H_
31 #define _DEV_IC_DP8573AREG_H_
34 * National Semiconductor DP8573A Real Time Clock
37 /* Control and Status Register Offsets and Masks */
38 #define DP8573A_STATUS 0x00 /* Main Status */
39 #define DP8573A_STATUS_INTSTAT 0x01 /* Interrupt Status */
40 #define DP8573A_STATUS_PWRFAIL 0x02 /* Power Fail Interrupt */
41 #define DP8573A_STATUS_PERINT 0x04 /* Period Interrupt */
42 #define DP8573A_STATUS_ALMINT 0x08 /* Alarm Interrupt */
43 #define DP8573A_STATUS_REGSEL 0x40 /* Register Select */
45 /* Register Select = 0 */
46 #define DP8573A_PFLAG 0x03 /* Periodic Flag */
47 #define DP8573A_PFLAG_MIN 0x01 /* Minutes */
48 #define DP8573A_PFLAG_10SEC 0x02 /* Ten Second */
49 #define DP8573A_PFLAG_SEC 0x04 /* Seconds */
50 #define DP8573A_PFLAG_100MIL 0x08 /* 100 Millisecond */
51 #define DP8573A_PFLAG_10MIL 0x10 /* 10 Millisecond */
52 #define DP8573A_PFLAG_MIL 0x20 /* Milliseconds */
53 #define DP8573A_PFLAG_OFSS 0x40 /* Oscillator Fail/Single Supply */
54 #define DP8573A_PFLAG_TESTMODE 0x80 /* Test Mode Enable */
56 #define DP8573A_TIMESAVE_CTL 0x04 /* Time Save Control */
57 #define DP8573A_TIMESAVE_CTL_EN 0x80 /* Time Save Enable */
59 /* Register Select = 1 */
60 #define DP8573A_RT_MODE 0x01 /* Real Time Mode */
61 #define DP8573A_RT_MODE_LYLSB 0x01 /* Leap Year LSB */
62 #define DP8573A_RT_MODE_LYMSB 0x02 /* Leap Year MSB */
63 #define DP8573A_RT_MODE_1224 0x04 /* 12(low)/24(high) Hour Mode */
64 #define DP8573A_RT_MODE_CLKSS 0x08 /* Clock Start(low)/Stop(high) */
65 #define DP8573A_RT_MODE_INTPFOP 0x10 /* Interrupt PF Operation */
67 #define DP8573A_OUT_MODE 0x02 /* Output Mode */
68 #define DP8573A_OUT_MODE_MFOPO 0x80 /* MFO Pin as Oscillator */
70 #define DP8573A_INT0_CTL 0x03 /* Interrupt Control 0 */
71 #define DP8573A_INT0_CTL_MIN 0x01 /* Minutes Enable */
72 #define DP8573A_INT0_CTL_10SEC 0x02 /* 10 Second Enable */
73 #define DP8573A_INT0_CTL_SEC 0x04 /* Seconds Enable */
74 #define DP8573A_INT0_CTL_100MIL 0x08 /* 100 Millisecond Enable */
75 #define DP8573A_INT0_CTL_10MIL 0x10 /* 10 Millisecond Enable */
76 #define DP8573A_INT0_CTL_MIL 0x20 /* Millisecond Enable */
78 #define DP8573A_INT1_CTL 0x04 /* Interrupt Control 1 */
79 #define DP8573A_INT1_CTL_SECC 0x01 /* Second Compare Enable */
80 #define DP8573A_INT1_CTL_MINC 0x02 /* Minute Compare Enable */
81 #define DP8573A_INT1_CTL_HOURC 0x04 /* Hour Compare Enable */
82 #define DP8573A_INT1_CTL_DOMC 0x08 /* Day of Month Compare Enable */
83 #define DP8573A_INT1_CTL_MONTHC 0x10 /* Month Compare Enable */
84 #define DP8573A_INT1_CTL_DOWC 0x20 /* Day of Week Compare Enable */
85 #define DP8573A_INT1_CTL_ALMINT 0x40 /* Alarm Interrupt Enable */
86 #define DP8573A_INT1_CTL_PWRINT 0x80 /* Power Fail Interrupt Enable */
88 /* Clock Counter Offsets */
89 #define DP8573A_COUNTERS 0x05 /* Start of Clock Counters */
90 #define DP8573A_SUBSECOND 0x05 /* 1/100 Second */
91 #define DP8573A_SECOND 0x06 /* Seconds */
92 #define DP8573A_MINUTE 0x07 /* Minutes */
93 #define DP8573A_HOUR 0x08 /* Hours */
94 #define DP8573A_DOM 0x09 /* Day of Month */
95 #define DP8573A_MONTH 0x0a /* Months */
96 #define DP8573A_YEAR 0x0b /* Years */
97 #define DP8573A_DOW 0x0e /* Day of Week */
99 /* Comparsion Registers */
100 #define DP8573A_CMP_SEC 0x13 /* Seconds */
101 #define DP8573A_CMP_MIN 0x14 /* Minutes */
102 #define DP8573A_CMP_HOUR 0x15 /* Hours */
103 #define DP8573A_CMP_DOM 0x16 /* Day of Month */
104 #define DP8573A_CMP_MONTH 0x17 /* Months */
105 #define DP8573A_CMP_DOW 0x18 /* Day of Week */
107 /* Time Save Registers */
108 #define DP8573A_SAVE_SEC 0x19 /* Seconds */
109 #define DP8573A_SAVE_MIN 0x1a /* Minutes */
110 #define DP8573A_SAVE_HOUR 0x1b /* Hours */
111 #define DP8573A_SAVE_DOM 0x1c /* Day of Month */
112 #define DP8573A_SAVE_MONTH 0x1d /* Months */
115 #define DP8573A_RAM_0C 0x0c /* RAM */
116 #define DP8573A_RAM_1E 0x1e /* RAM */
117 #define DP8573A_RAM_1F 0x1f /* RAM */
119 /* 12/24 Hour Masks */
120 #define DP8573A_HOUR_12HR_MASK 0x1f
121 #define DP8573A_HOUR_24HR_MASK 0x3f
123 #endif /* !_DEV_IC_DP8573AREG_H_ */
