sys/arch/sgimips/dev/int2reg.h

   1 /*      $NetBSD: int2reg.h,v 1.4 2005/12/11 12:18:52 christos Exp $     */
   2
   3 /*
   4  * Copyright (c) 2004 Christopher SEKIYA
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  * 3. The name of the author may not be used to endorse or promote products
  16  *    derived from this software without specific prior written permission.
  17  *
  18  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  19  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  20  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  21  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  22  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  23  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  27  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28  */
  29
  30 #if !defined(_ARCH_SGIMIPS_DEV_INT2_H_)
  31 #define _ARCH_SGIMIPS_DEV_INT2_H_
  32
  33 /* The INT has known locations on all SGI machines */
  34 #define INT2_IP12               0x1fb801c0
  35 #define INT2_IP20               0x1fb801c0
  36 #define INT2_IP22               0x1fbd9000
  37 #define INT2_IP24               0x1fbd9880
  38
  39 /* The following registers are all 8 bit. */
  40 #define INT2_LOCAL0_STATUS      0x03
  41 #define INT2_LOCAL0_STATUS_FIFO 0x01
  42 #define INT2_LOCAL0_MASK        0x07
  43 #define INT2_LOCAL1_STATUS      0x0b
  44 #define INT2_LOCAL1_MASK        0x0f
  45 #define INT2_MAP_STATUS         0x13
  46 #define INT2_MAP_MASK0          0x17
  47 #define INT2_MAP_MASK1          0x1b
  48 #define INT2_MAP_POL            0x1f
  49 #define INT2_TIMER_CLEAR        0x23
  50 #define INT2_ERROR_STATUS       0x27
  51 #define INT2_TIMER_0            0x33
  52 #define INT2_TIMER_1            0x37
  53 #define INT2_TIMER_2            0x3b
  54 #define INT2_TIMER_CONTROL      0x3f
  55
  56 #endif /* _ARCH_SGIMIPS_DEV_INT2_H_ */
  57