sys/arch/sgimips/dev/pic.c

   1 /*      $NetBSD: pic.c,v 1.12 2006/12/27 15:56:26 rumble Exp $   */
   2
   3 /*
   4  * Copyright (c) 2002 Steve Rumble
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  * 3. The name of the author may not be used to endorse or promote products
  16  *    derived from this software without specific prior written permission.
  17  *
  18  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  19  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  20  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  21  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  22  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  23  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  27  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28  */
  29
  30 #include <sys/cdefs.h>
  31 __KERNEL_RCSID(0, "$NetBSD: pic.c,v 1.12 2006/12/27 15:56:26 rumble Exp $");
  32
  33 #include <sys/param.h>
  34 #include <sys/device.h>
  35 #include <sys/systm.h>
  36
  37 #include <machine/cpu.h>
  38 #include <machine/locore.h>
  39 #include <machine/autoconf.h>
  40 #include <machine/bus.h>
  41 #include <machine/machtype.h>
  42 #include <machine/sysconf.h>
  43
  44 #include <sgimips/dev/picreg.h>
  45
  46 #include <sgimips/gio/giovar.h>
  47
  48 #include "locators.h"
  49
  50 struct pic_softc {
  51         struct device           sc_dev;
  52
  53         bus_space_tag_t         iot;
  54         bus_space_handle_t      ioh;
  55
  56 };
  57
  58 static int      pic_match(struct device *, struct cfdata *, void *);
  59 static void     pic_attach(struct device *, struct device *, void *);
  60 static int      pic_print(void *, const char *);
  61 static void     pic_bus_reset(void);
  62 static void     pic_bus_error(uint32_t, uint32_t, uint32_t, uint32_t);
  63 static void     pic_watchdog_enable(void);
  64 static void     pic_watchdog_disable(void);
  65 static void     pic_watchdog_tickle(void);
  66
  67 CFATTACH_DECL(pic, sizeof(struct pic_softc),
  68     pic_match, pic_attach, NULL, NULL);
  69
  70 struct pic_attach_args {
  71         const char             *iaa_name;
  72
  73         bus_space_tag_t         iaa_st;
  74         bus_space_handle_t      iaa_sh;
  75 };
  76
  77 int pic_gio32_arb_config(int, uint32_t);
  78
  79 static struct pic_softc psc;
  80
  81 static int
  82 pic_match(struct device * parent, struct cfdata * match, void *aux)
  83 {
  84         /*
  85          * PIC exists on IP12 systems. It appears to be the immediate
  86          * ancestor of the mc, for mips1 processors.
  87          */
  88         if (mach_type == MACH_SGI_IP12)
  89                 return 1;
  90         else
  91                 return 0;
  92 }
  93
  94 static void
  95 pic_attach(struct device * parent, struct device * self, void *aux)
  96 {
  97         uint32_t reg;
  98         struct pic_attach_args iaa;
  99         struct mainbus_attach_args *ma = aux;
 100
 101         psc.iot = SGIMIPS_BUS_SPACE_HPC;
 102         if (bus_space_map(psc.iot, ma->ma_addr, 0,
 103                           BUS_SPACE_MAP_LINEAR, &psc.ioh))
 104                 panic("pic_attach: could not allocate memory\n");
 105
 106         platform.bus_reset = pic_bus_reset;
 107         platform.watchdog_enable = pic_watchdog_enable;
 108         platform.watchdog_disable = pic_watchdog_disable;
 109         platform.watchdog_reset = pic_watchdog_tickle;
 110
 111         reg = bus_space_read_4(psc.iot, psc.ioh, PIC_SYSID);
 112         reg = (reg >> PIC_SYSID_REVSHIFT) & PIC_SYSID_REVMASK;
 113         printf("\npic0: Revision %c", reg + 64);
 114
 115         /* enable refresh, set big-endian, memory parity, allow slave access */
 116         reg = bus_space_read_4(psc.iot, psc.ioh, PIC_CPUCTRL);
 117         reg |= (PIC_CPUCTRL_REFRESH | PIC_CPUCTRL_BIGENDIAN | PIC_CPUCTRL_MPR |
 118                 PIC_CPUCTRL_SLAVE);
 119         bus_space_write_4(psc.iot, psc.ioh, PIC_CPUCTRL, reg);
 120
 121         /* query the mode register to see what's going on */
 122         reg = bus_space_read_4(psc.iot, psc.ioh, PIC_MODE);
 123         printf(": dblk (0x%x), iblk (0x%x)\n", reg & PIC_MODE_DBSIZ,
 124                reg & PIC_MODE_IBSIZ);
 125
 126         /* display the machine type, board revision */
 127         printf("pic0: ");
 128
 129         switch (mach_subtype) {
 130         case MACH_SGI_IP12_4D_3X:
 131                 printf("Personal Iris 4D/3x");
 132                 break;
 133         case MACH_SGI_IP12_VIP12:
 134                 printf("VME IP12");
 135                 break;
 136         case MACH_SGI_IP12_HP1:
 137                 printf("Indigo R3000");
 138                 break;
 139         case MACH_SGI_IP12_HPLC:
 140                 printf("Hollywood Light");
 141                 break;
 142         default:
 143                 printf("unknown machine");
 144                 break;
 145         }
 146         printf(", board revision %x\n", mach_boardrev);
 147
 148         printf("pic0: ");
 149
 150         if (reg & PIC_MODE_NOCACHE)
 151                 printf("cache disabled");
 152         else
 153                 printf("cache enabled");
 154
 155         if (reg & PIC_MODE_ISTREAM)
 156                 printf(", instr streaming");
 157
 158         if (reg & PIC_MODE_STOREPARTIAL)
 159                 printf(", store partial");
 160
 161         if (reg & PIC_MODE_BUSDRIVE)
 162                 printf(", bus drive");
 163
 164         /* gio32 allow master, real time devices */
 165         reg = bus_space_read_4(psc.iot, psc.ioh, PIC_GIO32ARB_SLOT0);
 166         reg &= ~(PIC_GIO32ARB_SLOT_SLAVE | PIC_GIO32ARB_SLOT_LONG);
 167         bus_space_write_4(psc.iot, psc.ioh, PIC_GIO32ARB_SLOT0, reg);
 168
 169         reg = bus_space_read_4(psc.iot, psc.ioh, PIC_GIO32ARB_SLOT1);
 170         reg &= ~(PIC_GIO32ARB_SLOT_SLAVE | PIC_GIO32ARB_SLOT_LONG);
 171         bus_space_write_4(psc.iot, psc.ioh, PIC_GIO32ARB_SLOT1, reg);
 172
 173         /* default gio32 burst time */
 174         bus_space_write_4(psc.iot, psc.ioh, PIC_GIO32ARB_BURST,
 175                           PIC_GIO32ARB_DEFBURST);
 176
 177         /* default gio32 delay time */
 178         bus_space_write_4(psc.iot, psc.ioh, PIC_GIO32ARB_DELAY,
 179                           PIC_GIO32ARB_DEFDELAY);
 180
 181         printf("\n");
 182
 183         platform.intr5 = pic_bus_error;
 184
 185         /*
 186          * A GIO bus exists on all IP12's. However, Personal Iris
 187          * machines use VME for their expansion bus.
 188          */
 189         iaa.iaa_name = "gio";
 190         (void)config_found(self, (void *)&iaa, pic_print);
 191
 192         pic_watchdog_enable();
 193 }
 194
 195
 196 static int
 197 pic_print(void *aux, const char *name)
 198 {
 199         struct pic_attach_args *iaa = aux;
 200
 201         if (name)
 202                 aprint_normal("%s at %s", iaa->iaa_name, name);
 203
 204         return UNCONF;
 205 }
 206
 207 static void
 208 pic_bus_reset(void)
 209 {
 210
 211         bus_space_write_4(psc.iot, psc.ioh, PIC_PARITY_ERROR, 0);
 212 }
 213
 214 static void
 215 pic_bus_error(uint32_t status, uint32_t cause, uint32_t pc, uint32_t ipending)
 216 {
 217
 218         printf("pic0: bus error\n");
 219         pic_bus_reset();
 220 }
 221
 222 static void
 223 pic_watchdog_enable(void)
 224 {
 225         uint32_t reg;
 226
 227         reg = bus_space_read_4(psc.iot, psc.ioh, PIC_CPUCTRL);
 228         reg |= PIC_CPUCTRL_WDOG;
 229         bus_space_write_4(psc.iot, psc.ioh, PIC_CPUCTRL, reg);
 230 }
 231
 232 static void
 233 pic_watchdog_disable(void)
 234 {
 235         uint32_t reg;
 236
 237         reg = bus_space_read_4(psc.iot, psc.ioh, PIC_CPUCTRL);
 238         reg &= ~(PIC_CPUCTRL_WDOG);
 239         bus_space_write_4(psc.iot, psc.ioh, PIC_CPUCTRL, reg);
 240 }
 241
 242 static void
 243 pic_watchdog_tickle(void)
 244 {
 245
 246         pic_watchdog_disable();
 247         pic_watchdog_enable();
 248 }
 249
 250 /* intended to be called from gio/gio.c only */
 251 int
 252 pic_gio32_arb_config(int slot, uint32_t flags)
 253 {
 254         uint32_t reg;
 255
 256         /* only Indigo machines have GIO expansion slots (XXX HPLC?) */
 257         if (mach_subtype != MACH_SGI_IP12_HP1 &&
 258             mach_subtype != MACH_SGI_IP12_HPLC)
 259                 return EINVAL;
 260
 261         /* graphics slot is not valid on IP12 */
 262         if (slot != GIO_SLOT_EXP0 && slot != GIO_SLOT_EXP1)
 263                 return EINVAL;
 264
 265         reg = bus_space_read_4(psc.iot, psc.ioh, (slot == GIO_SLOT_EXP0) ?
 266             PIC_GIO32ARB_SLOT0 : PIC_GIO32ARB_SLOT1);
 267
 268         if (flags & GIO_ARB_RT)
 269                 reg &= ~PIC_GIO32ARB_SLOT_LONG;
 270
 271         if (flags & GIO_ARB_LB)
 272                 reg |= PIC_GIO32ARB_SLOT_LONG;
 273
 274         if (flags & GIO_ARB_MST)
 275                 reg &= ~PIC_GIO32ARB_SLOT_SLAVE;
 276
 277         if (flags & GIO_ARB_SLV)
 278                 reg |= PIC_GIO32ARB_SLOT_SLAVE;
 279
 280         bus_space_write_4(psc.iot, psc.ioh, (slot == GIO_SLOT_EXP0) ?
 281             PIC_GIO32ARB_SLOT0 : PIC_GIO32ARB_SLOT1, reg);
 282
 283         return 0;
 284 }