1 /* $NetBSD: picreg.h,v 1.4 2005/12/11 12:18:52 christos Exp $ */
4 * Copyright (c) 2002 Steve Rumble
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 #ifndef _ARCH_SGIMIPS_DEV_PICREG_H_
31 #define _ARCH_SGIMIPS_DEV_PICREG_H_
33 #define PIC_CPUCTRL 0x00 /* CPU control */
35 #define PIC_CPUCTRL_REFRESH 0x0001 /* refresh enable */
36 #define PIC_CPUCTRL_BIGENDIAN 0x0002 /* big endian mode */
37 #define PIC_CPUCTRL_DBREFILL 0x0004 /* data block refill */
38 #define PIC_CPUCTRL_IBREFILL 0x0008 /* instruction block refill */
39 #define PIC_CPUCTRL_GDMAINTR 0x0010 /* gfx intr on completion */
40 #define PIC_CPUCTRL_GDMASYNC 0x0020 /* gfx dma sync */
41 #define PIC_CPUCTRL_FREFRESH 0x0040 /* fast refresh on 33 MHz+ gio */
42 #define PIC_CPUCTRL_NOVMEERR 0x0080 /* disables vme bus errors */
43 #define PIC_CPUCTRL_FREFRESHB 0x0080 /* fast refresh on revs. a+b */
44 #define PIC_CPUCTRL_GR2 0x0100 /* gio gr2 mode (?) */
45 #define PIC_CPUCTRL_SYSRESET 0x0200 /* vme sysreset line */
46 #define PIC_CPUCTRL_MPR 0x0400 /* memory read parity enable */
47 #define PIC_CPUCTRL_SLAVE 0x0800 /* slave accesses permitted */
48 #define PIC_CPUCTRL_VMEARB 0x1000 /* vme arbiter enable */
49 #define PIC_CPUCTRL_WPR 0x2000 /* write bad parity */
50 #define PIC_CPUCTRL_WDOG 0x4000 /* watchdog enable */
51 #define PIC_CPUCTRL_GFXRESET 0x8000 /* reset graphics */
53 #define PIC_MODE 0x04 /* system mode */
55 #define PIC_MODE_DBSIZ 0x0003 /* data block size */
56 #define PIC_MODE_IBSIZ 0x000c /* instruction block size */
57 #define PIC_MODE_ISTREAM 0x0010 /* instruction streaming */
58 #define PIC_MODE_NOCACHE 0x0020 /* cache disabled */
59 #define PIC_MODE_STOREPARTIAL 0x0040 /* store partial */
60 #define PIC_MODE_BUSDRIVE 0x0080 /* bus drive */
62 #define PIC_SYSID 0x08 /* system id */
64 #define PIC_SYSID_FPU 0x0001 /* fpu exists */
65 #define PIC_SYSID_GDMAERR 0x0004 /* graphics dma error */
66 #define PIC_SYSID_GDMADONE 0x0008 /* graphics dma complete */
67 #define PIC_SYSID_VMERMW 0x0010 /* vme read-mod-write */
68 #define PIC_SYSID_REVSHIFT 0x0006 /* Rev bits shifted */
69 #define PIC_SYSID_REVMASK 0x0007 /* PIC revision */
71 #define PIC_MEMCFG0 0x10000 /* memory config register 0 */
72 #define PIC_MEMCFG1 0x10004 /* memory config register 1 */
73 #define PIC_MEMCFG0_PHYSADDR (0x1fa00000 + PIC_MEMCFG0)
74 #define PIC_MEMCFG1_PHYSADDR (0x1fa00000 + PIC_MEMCFG1)
76 #define PIC_MEMCFG_4MB 0x0000 /* 4 megabytes (never occurs) */
77 #define PIC_MEMCFG_8MB 0x0001 /* 8 megabytes */
78 #define PIC_MEMCFG_16MB 0x0003 /* 16 megabytes */
79 #define PIC_MEMCFG_32MB 0x0007 /* 32 megabytes */
80 #define PIC_MEMCFG_64MB 0x000f /* 64 megabytes */
82 #define PIC_MEMCFG_BADSIZ 0x0000 /* bad memory size */
83 #define PIC_MEMCFG_ADDRMASK 0x003f /* memory address mask */
84 #define PIC_MEMCFG_BADADDR 0x003f /* no memory in bank */
85 #define PIC_MEMCFG_SIZMASK 0x0f00 /* bank size mask */
88 * The bank memory address is computed the same way mc's is.
89 * Size is similar, only having one less bit (max. 64MB per bank).
91 #define PIC_MEMCFG_ADDR(x) \
92 ((x & PIC_MEMCFG_ADDRMASK) << 22)
93 #define PIC_MEMCFG_SIZ(x) \
94 (((x & PIC_MEMCFG_SIZMASK) + 0x100) << 14)
96 #define PIC_WRONLY_REFRESH 0x10100 /* write only refresh timer */
98 #define PIC_PARITY_ERROR 0x10200 /* parity errors */
100 #define PIC_PARITY_ERROR_GDMA 0x0001 /* graphics dma */
101 #define PIC_PARITY_ERROR_DMA 0x0002
102 #define PIC_PARITY_ERROR_CPU 0x0004
103 #define PIC_PARITY_ERROR_VME 0x0008
104 #define PIC_PARITY_ERROR_BYTE3 0x0010 /* error in fourth byte */
105 #define PIC_PARITY_ERROR_BYTE2 0x0020 /* error in third byte */
106 #define PIC_PARITY_ERROR_BYTE1 0x0040 /* error in second byte */
107 #define PIC_PARITY_ERROR_BYTE0 0x0080 /* error in first byte */
109 #define PIC_PARITY_ADDR_CPU 0x10204 /* cpu error address */
110 #define PIC_PARITY_ADDR_DMA 0x10208 /* dma error address */
111 #define PIC_PARITY_ERROR_CLEAR 0x10210 /* clear parity errors */
114 * GIO slot configuration registers described by the 'GIO BUS Specification'
115 * apparently no IP20 counterpart on mc.
117 #define PIC_GIO32ARB_SLOT0 0x20000 /* set slot 0 config */
118 #define PIC_GIO32ARB_SLOT1 0x20004 /* set slot 1 config */
120 #define PIC_GIO32ARB_SLOT_SLAVE 0x0001 /* slave only */
121 #define PIC_GIO32ARB_SLOT_LONG 0x0002 /* long burst */
123 #define PIC_GIO32ARB_BURST 0x20008 /* set gio burst */
125 #define PIC_GIO32ARB_DEFBURST 0x0001 /* default burst value */
127 #define PIC_GIO32ARB_DELAY 0x2000c /* set gio delay */
129 #define PIC_GIO32ARB_DEFDELAY 0x00f2 /* default delay value */
131 #endif /* _ARCH_SGIMIPS_DEV_PICREG_H_ */
