sys/arch/sgimips/hpc/haltworeg.h

   1 /* $NetBSD: haltworeg.h,v 1.1.4.3 2004/09/21 13:21:19 skrll Exp $ */
   2
   3 /*
   4  * Copyright (c) 2003 Ilpo Ruotsalainen
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  * 3. The name of the author may not be used to endorse or promote products
  16  *    derived from this software without specific prior written permission.
  17  *
  18  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  19  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  20  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  21  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  22  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  23  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  27  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28  *
  29  * <<Id: LICENSE_GC,v 1.1 2001/10/01 23:24:05 cgd Exp>>
  30  */
  31
  32 #ifndef _ARCH_SGIMIPS_HPC_HALTWOREG_H_
  33 #define _ARCH_SGIMIPS_HPC_HALTWOREG_H_
  34
  35 /* HAL2 direct-addressable registers, PBUS PIO channel 0 */
  36 #define HAL2_REG_CTL_ISR                0x10
  37
  38 #define HAL2_REG_CTL_REV                0x20
  39 #define  HAL2_REV_AUDIO_PRESENT_N       0x8000
  40
  41 #define HAL2_REG_CTL_IAR                0x30
  42 #define  HAL2_IAR_READ                  0x0080
  43
  44 #define HAL2_REG_CTL_IDR0               0x40
  45 #define HAL2_REG_CTL_IDR1               0x50
  46 #define HAL2_REG_CTL_IDR2               0x60
  47 #define HAL2_REG_CTL_IDR3               0x70
  48
  49 #define HAL2_ISR_TSTATUS                0x01
  50 #define  HAL2_ISR_GLOBAL_RESET_N        0x08
  51 #define  HAL2_ISR_CODEC_RESET_N         0x10
  52
  53 /* HAL2 direct-addressable registers, PBUS PIO channel 2 */
  54 #define HAL2_REG_VOL_RIGHT              0x00
  55 #define HAL2_REG_VOL_LEFT               0x04
  56
  57 /* HAL2 indirect-addressable registers */
  58 #define HAL2_IREG_RELAY_C               0x9100
  59 #define  HAL2_RELAY_C_STATE             0x01
  60
  61 #define HAL2_IREG_DMA_PORT_EN           0x9104
  62 #define  HAL2_DMA_PORT_EN_CODECTX       0x08
  63
  64 #define HAL2_IREG_DMA_END               0x9108
  65 #define  HAL2_DMA_END_CODECTX           0x08
  66
  67 #define HAL2_IREG_DMA_DRV               0x910C
  68
  69 #define HAL2_IREG_BRES1_C1              0x2104
  70 #define HAL2_IREG_BRES1_C2              0x2108
  71
  72 #define HAL2_IREG_DAC_C1                0x1404
  73 #define  HAL2_C1_DMA_SHIFT              0
  74 #define  HAL2_C1_CLKID_SHIFT            3
  75 #define  HAL2_C1_DATAT_SHIFT            8
  76
  77 #define HAL2_IREG_DAC_C2                0x1408
  78
  79 #endif