sys/arch/sgimips/mace/if_mecreg.h

   1 /*      $NetBSD: if_mecreg.h,v 1.3 2005/12/10 07:05:10 tsutsui Exp $    */
   2
   3 /*
   4  * Copyright (c) 2001 Christopher Sekiya
   5  * Copyright (c) 2000 Soren S. Jorvang
   6  * All rights reserved.
   7  *
   8  * Redistribution and use in source and binary forms, with or without
   9  * modification, are permitted provided that the following conditions
  10  * are met:
  11  * 1. Redistributions of source code must retain the above copyright
  12  *    notice, this list of conditions and the following disclaimer.
  13  * 2. Redistributions in binary form must reproduce the above copyright
  14  *    notice, this list of conditions and the following disclaimer in the
  15  *    documentation and/or other materials provided with the distribution.
  16  * 3. All advertising materials mentioning features or use of this software
  17  *    must display the following acknowledgement:
  18  *          This product includes software developed for the
  19  *          NetBSD Project.  See http://www.NetBSD.org/ for
  20  *          information about NetBSD.
  21  * 4. The name of the author may not be used to endorse or promote products
  22  *    derived from this software without specific prior written permission.
  23  *
  24  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  25  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  26  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  27  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  28  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  29  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  30  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  31  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  32  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  33  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  34  */
  35
  36 /*
  37  * MACE MAC110 ethernet register definitions
  38  */
  39
  40 #define MEC_MAC_CONTROL                 0x00
  41 #define  MEC_MAC_CORE_RESET             0x0000000000000001 /* reset signal */
  42 #define  MEC_MAC_FULL_DUPLEX            0x0000000000000002 /* 1 to enable */
  43 #define  MEC_MAC_INT_LOOPBACK           0x0000000000000004 /* 0 = normal op */
  44 #define  MEC_MAC_SPEED_SELECT           0x0000000000000008 /* 0/1 10/100 */
  45 #define  MEC_MAC_MII_SELECT             0x0000000000000010 /* MII/SIA */
  46 #define  MEC_MAC_FILTER_MASK            0x0000000000000060
  47 #define  MEC_MAC_FILTER_STATION         0x0000000000000000
  48 #define  MEC_MAC_FILTER_MATCHMULTI      0x0000000000000020
  49 #define  MEC_MAC_FILTER_ALLMULTI        0x0000000000000040
  50 #define  MEC_MAC_FILTER_PROMISC         0x0000000000000060
  51 #define  MEC_MAC_LINK_FAILURE           0x0000000000000080
  52 #define  MEC_MAC_IPGT                   0x0000000000007f00 /* interpacket gap */
  53 #define  MEC_MAC_IPGT_SHIFT             8
  54 #define  MEC_MAC_IPGR1                  0x00000000003f8000
  55 #define  MEC_MAC_IPGR1_SHIFT            15
  56 #define  MEC_MAC_IPGR2                  0x000000001fc00000
  57 #define  MEC_MAC_IPGR2_SHIFT            22
  58 #define  MEC_MAC_REVISION               0x00000000e0000000
  59 #define  MEC_MAC_REVISION_SHIFT         29
  60
  61 #define MEC_MAC_IPG_DEFAULT                                             \
  62         (21 << MEC_MAC_IPGT_SHIFT) |                                    \
  63         (17 << MEC_MAC_IPGR1_SHIFT) |                                   \
  64         (11 << MEC_MAC_IPGR2_SHIFT)
  65
  66 #define MEC_INT_STATUS                  0x08
  67 #define  MEC_INT_STATUS_MASK            0x00000000000000ff
  68 #define  MEC_INT_TX_EMPTY               0x0000000000000001
  69 #define  MEC_INT_TX_PACKET_SENT         0x0000000000000002
  70 #define  MEC_INT_TX_LINK_FAIL           0x0000000000000004
  71 #define  MEC_INT_TX_MEM_ERROR           0x0000000000000008
  72 #define  MEC_INT_TX_ABORT               0x0000000000000010
  73 #define  MEC_INT_RX_THRESHOLD           0x0000000000000020
  74 #define  MEC_INT_RX_FIFO_UNDERFLOW      0x0000000000000040
  75 #define  MEC_INT_RX_DMA_UNDERFLOW       0x0000000000000080
  76 #define  MEC_INT_RX_MCL_FIFO_ALIAS      0x0000000000001f00
  77 #define  MEC_INT_RX_MCL_FIFO_SHIFT      8
  78 #define  MEC_INT_TX_RING_BUFFER_ALIAS   0x0000000001ff0000
  79 #define  MEC_INT_TX_RING_BUFFER_SHIFT   16
  80 #define  MEC_INT_RX_SEQUENCE_NUMBER     0x000000003e000000
  81 #define  MEC_INT_MCAST_HASH_OUTPUT      0x0000000040000000
  82
  83 #define MEC_DMA_CONTROL                 0x10
  84 #define  MEC_DMA_TX_INT_ENABLE          0x0000000000000001
  85 #define  MEC_DMA_TX_DMA_ENABLE          0x0000000000000002
  86 #define  MEC_DMA_TX_RING_SIZE_MASK      0x000000000000000c
  87 #define  MEC_DMA_RX_INT_THRESHOLD       0x00000000000001f0
  88 #define  MEC_DMA_RX_INT_THRESH_SHIFT    4
  89 #define  MEC_DMA_RX_INT_ENABLE          0x0000000000000200
  90 #define  MEC_DMA_RX_RUNT                0x0000000000000400
  91 #define  MEC_DMA_RX_PACKET_GATHER       0x0000000000000800
  92 #define  MEC_DMA_RX_DMA_OFFSET          0x0000000000007000
  93 #define  MEC_DMA_RX_DMA_OFFSET_SHIFT    12
  94 #define  MEC_DMA_RX_DMA_ENABLE          0x0000000000008000
  95
  96 #define MEC_TIMER                       0x18
  97 #define MEC_TX_ALIAS                    0x20
  98 #define  MEC_TX_ALIAS_INT_ENABLE        0x0000000000000001
  99
 100 #define MEC_RX_ALIAS                    0x28
 101 #define  MEC_RX_ALIAS_INT_ENABLE        0x0000000000000200
 102 #define  MEC_RX_ALIAS_INT_THRESHOLD     0x00000000000001f0
 103
 104 #define MEC_TX_RING_PTR                 0x30
 105 #define  MEC_TX_RING_WRITE_PTR          0x00000000000001ff
 106 #define  MEC_TX_RING_READ_PTR           0x0000000001ff0000
 107 #define MEC_TX_RING_PTR_ALIAS           0x38
 108
 109 #define MEC_RX_FIFO                     0x40
 110 #define  MEC_RX_FIFO_ELEMENT_COUNT      0x000000000000001f
 111 #define  MEC_RX_FIFO_READ_PTR           0x0000000000000f00
 112 #define  MEC_RX_FIFO_GEN_NUMBER         0x0000000000001000
 113 #define  MEC_RX_FIFO_WRITE_PTR          0x00000000000f0000
 114 #define  MEC_RX_FIFO_GEN_NUMBER_2       0x0000000000100000
 115
 116 #define MEC_RX_FIFO_ALIAS1              0x48
 117 #define MEC_RX_FIFO_ALIAS2              0x50
 118 #define MEC_TX_VECTOR                   0x58
 119 #define MEC_IRQ_VECTOR                  0x58
 120
 121 #define MEC_PHY_DATA                    0x60
 122 #define  MEC_PHY_DATA_BUSY              0x00010000
 123 #define  MEC_PHY_DATA_VALUE             0x0000ffff
 124
 125 #define MEC_PHY_ADDRESS                 0x68
 126 #define  MEC_PHY_ADDR_REGISTER          0x0000001f
 127 #define  MEC_PHY_ADDR_DEVICE            0x000003e0
 128 #define  MEC_PHY_ADDR_DEVSHIFT          5
 129
 130 #define MEC_PHY_READ_INITIATE           0x70
 131 #define MEC_PHY_BACKOFF                 0x78
 132
 133 #define MEC_STATION                     0xa0
 134 #define MEC_STATION_ALT                 0xa8
 135 #define  MEC_STATION_MASK               0x0000ffffffffffffULL
 136
 137 #define MEC_MULTICAST                   0xb0
 138 #define MEC_TX_RING_BASE                0xb8
 139 #define MEC_TX_PKT1_CMD_1               0xc0
 140 #define MEC_TX_PKT1_BUFFER_1            0xc8
 141 #define MEC_TX_PKT1_BUFFER_2            0xd0
 142 #define MEC_TX_PKT1_BUFFER_3            0xd8
 143 #define MEC_TX_PKT2_CMD_1               0xe0
 144 #define MEC_TX_PKT2_BUFFER_1            0xe8
 145 #define MEC_TX_PKT2_BUFFER_2            0xf0
 146 #define MEC_TX_PKT2_BUFFER_3            0xf8
 147
 148 #define MEC_MCL_RX_FIFO                 0x100
 149