sys/arch/sgimips/mace/mace.c

   1 /*      $NetBSD: mace.c,v 1.15 2008/08/23 17:43:36 tsutsui Exp $        */
   2
   3 /*
   4  * Copyright (c) 2003 Christopher Sekiya
   5  * Copyright (c) 2002,2003 Rafal K. Boni
   6  * Copyright (c) 2000 Soren S. Jorvang
   7  * All rights reserved.
   8  *
   9  * Redistribution and use in source and binary forms, with or without
  10  * modification, are permitted provided that the following conditions
  11  * are met:
  12  * 1. Redistributions of source code must retain the above copyright
  13  *    notice, this list of conditions and the following disclaimer.
  14  * 2. Redistributions in binary form must reproduce the above copyright
  15  *    notice, this list of conditions and the following disclaimer in the
  16  *    documentation and/or other materials provided with the distribution.
  17  * 3. All advertising materials mentioning features or use of this software
  18  *    must display the following acknowledgement:
  19  *          This product includes software developed for the
  20  *          NetBSD Project.  See http://www.NetBSD.org/ for
  21  *          information about NetBSD.
  22  * 4. The name of the author may not be used to endorse or promote products
  23  *    derived from this software without specific prior written permission.
  24  *
  25  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  26  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  27  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  28  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  29  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  30  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  31  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  32  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  33  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  34  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  35  */
  36
  37 /*
  38  * O2 MACE
  39  *
  40  * The MACE is weird -- although it is a 32-bit device, writes only seem to
  41  * work properly if they are 64-bit-at-once writes (at least, out in ISA
  42  * space and probably MEC space -- the PCI stuff seems to be okay with _4).
  43  * Therefore, the _8* routines are used even though the top 32 bits are
  44  * thrown away.
  45  */
  46
  47 #include <sys/cdefs.h>
  48 __KERNEL_RCSID(0, "$NetBSD: mace.c,v 1.15 2008/08/23 17:43:36 tsutsui Exp $");
  49
  50 #include <sys/param.h>
  51 #include <sys/systm.h>
  52 #include <sys/device.h>
  53 #include <sys/callout.h>
  54 #include <sys/mbuf.h>
  55 #include <sys/malloc.h>
  56 #include <sys/kernel.h>
  57 #include <sys/socket.h>
  58 #include <sys/ioctl.h>
  59 #include <sys/errno.h>
  60 #include <sys/syslog.h>
  61
  62 #include <uvm/uvm_extern.h>
  63
  64 #define _SGIMIPS_BUS_DMA_PRIVATE
  65 #include <machine/bus.h>
  66 #include <machine/cpu.h>
  67 #include <machine/locore.h>
  68 #include <machine/autoconf.h>
  69 #include <machine/machtype.h>
  70
  71 #include <sgimips/mace/macevar.h>
  72 #include <sgimips/mace/macereg.h>
  73 #include <sgimips/dev/crimevar.h>
  74 #include <sgimips/dev/crimereg.h>
  75
  76 #include "locators.h"
  77
  78 #define MACE_NINTR 32 /* actually only 8, but interrupts are shared */
  79
  80 struct {
  81         unsigned int    irq;
  82         unsigned int    intrmask;
  83         int     (*func)(void *);
  84         void    *arg;
  85         struct evcnt evcnt;
  86         char    evname[32];
  87 } maceintrtab[MACE_NINTR];
  88
  89 struct mace_softc {
  90         struct device sc_dev;
  91
  92         bus_space_tag_t iot;
  93         bus_space_handle_t ioh;
  94         bus_dma_tag_t dmat; /* 32KB ring buffers, 4KB segments, for ISA  */
  95         int nsegs;
  96         bus_dma_segment_t seg;
  97         bus_dmamap_t map;
  98
  99         void *isa_ringbuffer;
 100 };
 101
 102 static int      mace_match(struct device *, struct cfdata *, void *);
 103 static void     mace_attach(struct device *, struct device *, void *);
 104 static int      mace_print(void *, const char *);
 105 static int      mace_search(struct device *, struct cfdata *,
 106                             const int *, void *);
 107
 108 CFATTACH_DECL(mace, sizeof(struct mace_softc),
 109     mace_match, mace_attach, NULL, NULL);
 110
 111 #if defined(BLINK)
 112 static callout_t mace_blink_ch;
 113 static void     mace_blink(void *);
 114 #endif
 115
 116 static int
 117 mace_match(struct device *parent, struct cfdata *match, void *aux)
 118 {
 119
 120         /*
 121          * The MACE is in the O2.
 122          */
 123         if (mach_type == MACH_SGI_IP32)
 124                 return 1;
 125
 126         return 0;
 127 }
 128
 129 static void
 130 mace_attach(struct device *parent, struct device *self, void *aux)
 131 {
 132         struct mace_softc *sc = (struct mace_softc *)self;
 133         struct mainbus_attach_args *ma = aux;
 134         uint32_t scratch;
 135
 136 #ifdef BLINK
 137         callout_init(&mace_blink_ch, 0);
 138 #endif
 139
 140         sc->iot = SGIMIPS_BUS_SPACE_MACE;
 141         sc->dmat = &sgimips_default_bus_dma_tag;
 142
 143         if (bus_space_map(sc->iot, ma->ma_addr, 0,
 144             BUS_SPACE_MAP_LINEAR, &sc->ioh))
 145                 panic("mace_attach: could not allocate memory\n");
 146
 147         aprint_normal("\n");
 148
 149         aprint_debug("%s: isa sts %#"PRIx64"\n", self->dv_xname,
 150             bus_space_read_8(sc->iot, sc->ioh, MACE_ISA_INT_STATUS));
 151         aprint_debug("%s: isa msk %#"PRIx64"\n", self->dv_xname,
 152             bus_space_read_8(sc->iot, sc->ioh, MACE_ISA_INT_MASK));
 153
 154         /*
 155          * Turn on most ISA interrupts.  These are actually masked and
 156          * registered via the CRIME, as the MACE ISA interrupt mask is
 157          * really whacky and nigh on impossible to map to a sane autoconfig
 158          * scheme.  We do, however, turn off the count/compare timer and RTC
 159          * interrupts as they are unused and conflict with the PS/2
 160          * keyboard and mouse interrupts.
 161          */
 162
 163         bus_space_write_8(sc->iot, sc->ioh, MACE_ISA_INT_MASK, 0xffff0aff);
 164         bus_space_write_8(sc->iot, sc->ioh, MACE_ISA_INT_STATUS, 0);
 165
 166         /* set up LED for solid green or blink, if that's your fancy */
 167         scratch = bus_space_read_8(sc->iot, sc->ioh, MACE_ISA_FLASH_NIC_REG);
 168         scratch |= MACE_ISA_LED_RED;
 169         scratch &= ~(MACE_ISA_LED_GREEN);
 170         bus_space_write_8(sc->iot, sc->ioh, MACE_ISA_FLASH_NIC_REG, scratch);
 171
 172 #if defined(BLINK)
 173         mace_blink(sc);
 174 #endif
 175
 176         /* Initialize the maceintr elements to sane values */
 177         for (scratch = 0; scratch < MACE_NINTR; scratch++) {
 178                 maceintrtab[scratch].func = NULL;
 179                 maceintrtab[scratch].irq = 0;
 180         }
 181
 182         config_search_ia(mace_search, self, "mace", NULL);
 183 }
 184
 185
 186 static int
 187 mace_print(void *aux, const char *pnp)
 188 {
 189         struct mace_attach_args *maa = aux;
 190
 191         if (pnp != 0)
 192                 return QUIET;
 193
 194         if (maa->maa_offset != MACECF_OFFSET_DEFAULT)
 195                 aprint_normal(" offset 0x%lx", maa->maa_offset);
 196         if (maa->maa_intr != MACECF_INTR_DEFAULT)
 197                 aprint_normal(" intr %d", maa->maa_intr);
 198         if (maa->maa_offset != MACECF_INTRMASK_DEFAULT)
 199                 aprint_normal(" intrmask 0x%x", maa->maa_intrmask);
 200
 201         return UNCONF;
 202 }
 203
 204 static int
 205 mace_search(struct device *parent, struct cfdata *cf,
 206             const int *ldesc, void *aux)
 207 {
 208         struct mace_softc *sc = (struct mace_softc *)parent;
 209         struct mace_attach_args maa;
 210         int tryagain;
 211
 212         do {
 213                 maa.maa_offset = cf->cf_loc[MACECF_OFFSET];
 214                 maa.maa_intr = cf->cf_loc[MACECF_INTR];
 215                 maa.maa_intrmask = cf->cf_loc[MACECF_INTRMASK];
 216                 maa.maa_st = SGIMIPS_BUS_SPACE_MACE;
 217                 maa.maa_sh = sc->ioh;   /* XXX */
 218                 maa.maa_dmat = &sgimips_default_bus_dma_tag;
 219                 maa.isa_ringbuffer = sc->isa_ringbuffer;
 220
 221                 tryagain = 0;
 222                 if (config_match(parent, cf, &maa) > 0) {
 223                         config_attach(parent, cf, &maa, mace_print);
 224                         tryagain = (cf->cf_fstate == FSTATE_STAR);
 225                 }
 226
 227         } while (tryagain);
 228
 229         return 0;
 230 }
 231
 232 void *
 233 mace_intr_establish(int intr, int level, int (*func)(void *), void *arg)
 234 {
 235         int i;
 236
 237         if (intr < 0 || intr >= 16)
 238                 panic("invalid interrupt number");
 239
 240         for (i = 0; i < MACE_NINTR; i++)
 241                 if (maceintrtab[i].func == NULL) {
 242                         maceintrtab[i].func = func;
 243                         maceintrtab[i].arg = arg;
 244                         maceintrtab[i].irq = (1 << intr);
 245                         maceintrtab[i].intrmask = level;
 246                         snprintf(maceintrtab[i].evname,
 247                             sizeof(maceintrtab[i].evname),
 248                             "intr %d level 0x%x", intr, level);
 249                         evcnt_attach_dynamic(&maceintrtab[i].evcnt,
 250                             EVCNT_TYPE_INTR, NULL,
 251                             "mace", maceintrtab[i].evname);
 252                         break;
 253                 }
 254
 255         crime_intr_mask(intr);
 256         aprint_debug("mace: established interrupt %d (level %x)\n",
 257             intr, level);
 258         return (void *)&maceintrtab[i];
 259 }
 260
 261 void
 262 mace_intr_disestablish(void *cookie)
 263 {
 264         int intr = -1, level = 0, irq = 0, i;
 265
 266         for (i = 0; i < MACE_NINTR; i++)
 267                 if (&maceintrtab[i] == cookie) {
 268                         evcnt_detach(&maceintrtab[i].evcnt);
 269                         for (intr = 0;
 270                             maceintrtab[i].irq == (1 << intr); intr++);
 271                         level = maceintrtab[i].intrmask;
 272                         irq = maceintrtab[i].irq;
 273
 274                         maceintrtab[i].irq = 0;
 275                         maceintrtab[i].intrmask = 0;
 276                         maceintrtab[i].func = NULL;
 277                         maceintrtab[i].arg = NULL;
 278                         memset(&maceintrtab[i].evcnt, 0, sizeof (struct evcnt));
 279                         memset(&maceintrtab[i].evname, 0,
 280                             sizeof (maceintrtab[i].evname));
 281                         break;
 282                 }
 283         if (intr == -1)
 284                 panic("mace: lost maceintrtab");
 285
 286         /* do not do an unmask when irq is shared. */
 287         for (i = 0; i < MACE_NINTR; i++)
 288                 if (&maceintrtab[i].func != NULL && maceintrtab[i].irq == irq)
 289                         break;
 290         if (i == MACE_NINTR)
 291                 crime_intr_unmask(intr);
 292         aprint_debug("mace: disestablished interrupt %d (level %x)\n",
 293             intr, level);
 294 }
 295
 296 void
 297 mace_intr(int irqs)
 298 {
 299         uint64_t isa_irq, isa_mask;
 300         int i;
 301
 302         /* irq 4 is the ISA cascade interrupt.  Must handle with care. */
 303         if (irqs & (1 << 4)) {
 304                 isa_mask = mips3_ld((volatile uint64_t *)MIPS_PHYS_TO_KSEG1(MACE_BASE
 305                     + MACE_ISA_INT_MASK));
 306                 isa_irq = mips3_ld((volatile uint64_t *)MIPS_PHYS_TO_KSEG1(MACE_BASE
 307                     + MACE_ISA_INT_STATUS));
 308                 for (i = 0; i < MACE_NINTR; i++) {
 309                         if ((maceintrtab[i].irq == (1 << 4)) &&
 310                             (isa_irq & maceintrtab[i].intrmask)) {
 311                                 (maceintrtab[i].func)(maceintrtab[i].arg);
 312                                 maceintrtab[i].evcnt.ev_count++;
 313                         }
 314                 }
 315                 irqs &= ~(1 << 4);
 316         }
 317
 318         for (i = 0; i < MACE_NINTR; i++)
 319                 if ((irqs & maceintrtab[i].irq)) {
 320                         (maceintrtab[i].func)(maceintrtab[i].arg);
 321                         maceintrtab[i].evcnt.ev_count++;
 322                 }
 323 }
 324
 325 #if defined(BLINK)
 326 static void
 327 mace_blink(void *self)
 328 {
 329         struct mace_softc *sc = (struct mace_softc *) self;
 330         register int s;
 331         int value;
 332
 333         s = splhigh();
 334         value = bus_space_read_8(sc->iot, sc->ioh, MACE_ISA_FLASH_NIC_REG);
 335         value ^= MACE_ISA_LED_GREEN;
 336         bus_space_write_8(sc->iot, sc->ioh, MACE_ISA_FLASH_NIC_REG, value);
 337         splx(s);
 338         /*
 339          * Blink rate is:
 340          *      full cycle every second if completely idle (loadav = 0)
 341          *      full cycle every 2 seconds if loadav = 1
 342          *      full cycle every 3 seconds if loadav = 2
 343          * etc.
 344          */
 345         s = (((averunnable.ldavg[0] + FSCALE) * hz) >> (FSHIFT + 1));
 346         callout_reset(&mace_blink_ch, s, mace_blink, sc);
 347
 348 }
 349 #endif